From ff66ccefe51e5783855f7d4646ca491fbf12bb89 Mon Sep 17 00:00:00 2001 From: Jan Beulich Date: Mon, 27 May 2019 12:24:37 +0200 Subject: [PATCH] x86/CPUID: adjust SSEn dependencies Along the lines of b9f6395590 ("x86/cpuid: adjust dependencies of post-SSE ISA extensions") further convert SSEn dependencies to be more chain like, with each successor addition depending on its immediate predecessor. This is more in line with how hardware has involved, and how other projects like gcc and binutils connect things together. Signed-off-by: Jan Beulich Acked-by: Andrew Cooper --- xen/tools/gen-cpuid.py | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/xen/tools/gen-cpuid.py b/xen/tools/gen-cpuid.py index 8f6b977df0..1b49360455 100755 --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -196,18 +196,16 @@ def crunch_numbers(state): # instructions. Several futher instruction sets are built on core # %XMM support, without specific inter-dependencies. Additionally # AMD has a special mis-alignment sub-mode. - SSE: [SSE2, SSE3, SSSE3, SSE4A, MISALIGNSSE], + SSE: [SSE2, MISALIGNSSE], # SSE2 was re-specified as core instructions for 64bit. Also ISA # extensions dealing with vectors of integers are added here rather # than to SSE. - SSE2: [LM, AESNI, PCLMULQDQ, SHA], + SSE2: [SSE3, LM, AESNI, PCLMULQDQ, SHA], - # SSE4.1 explicitly depends on SSE3 and SSSE3 - SSE3: [SSE4_1], - SSSE3: [SSE4_1], - - # SSE4.2 explicitly depends on SSE4.1 + # Other SSEn each depend on their predecessor versions. + SSE3: [SSSE3], + SSSE3: [SSE4_1, SSE4A], SSE4_1: [SSE4_2], # AMD specify no relationship between POPCNT and SSE4.2. Intel -- 2.30.2