From efed19238c1bf3bb85989648a307ba3232ad96f4 Mon Sep 17 00:00:00 2001 From: Konrad Rzeszutek Wilk Date: Mon, 22 Aug 2016 11:20:03 -0400 Subject: [PATCH] xen/arm32: Add an helper to invalidate all instruction caches This is similar to commit fb9d877a9c0f3d4d15db8f6e0c5506ea641862c6 "xen/arm64: Add an helper to invalidate all instruction caches" except it is on ARM32 side. When we are flushing the cache we are most likely also want to flush the branch predictor too. Hence we add this. And we also need to follow this with dsb()/isb() which are memory barriers(). Reviewed-by: Julien Grall Signed-off-by: Konrad Rzeszutek Wilk --- xen/include/asm-arm/arm32/page.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/xen/include/asm-arm/arm32/page.h b/xen/include/asm-arm/arm32/page.h index bccdbfc945..ea4b312c70 100644 --- a/xen/include/asm-arm/arm32/page.h +++ b/xen/include/asm-arm/arm32/page.h @@ -29,6 +29,22 @@ static inline void write_pte(lpae_t *p, lpae_t pte) * inline asm operand) */ #define __clean_and_invalidate_dcache_one(R) STORE_CP32(R, DCCIMVAC) +/* + * Invalidate all instruction caches in Inner Shareable domain to PoU. + * We also need to flush the branch predictor for ARMv7 as it may be + * architecturally visible to the software (see B2.2.4 in ARM DDI 0406C.b). + */ +static inline void invalidate_icache(void) +{ + asm volatile ( + CMD_CP32(ICIALLUIS) /* Flush I-cache. */ + CMD_CP32(BPIALLIS) /* Flush branch predictor. */ + : : : "memory"); + + dsb(ish); /* Ensure completion of the flush I-cache */ + isb(); /* Synchronize fetched instruction stream. */ +} + /* * Flush all hypervisor mappings from the TLB and branch predictor of * the local processor. -- 2.30.2