From df6f5cd9e51e742b23dcee99907e97a435716061 Mon Sep 17 00:00:00 2001 From: Jan Beulich Date: Thu, 27 Jan 2022 13:50:19 +0100 Subject: [PATCH] x86/Intel: IceLake D + Sapphire Rapids Xeons also support PPIN This is as per Linux commits a331f5fdd36d ("x86/mce: Add Xeon Sapphire Rapids to list of CPUs that support PPIN") and [tip.git] e464121f2d40 ("x86/cpu: Add Xeon Icelake-D to list of CPUs that support PPIN"), just in case a subsequent change making use of the respective new CPUID bit doesn't cover either of these models. Signed-off-by: Jan Beulich Acked-by: Andrew Cooper --- xen/arch/x86/cpu/mcheck/mce_intel.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/xen/arch/x86/cpu/mcheck/mce_intel.c b/xen/arch/x86/cpu/mcheck/mce_intel.c index bb9f3a3ff7..d0161e9d4d 100644 --- a/xen/arch/x86/cpu/mcheck/mce_intel.c +++ b/xen/arch/x86/cpu/mcheck/mce_intel.c @@ -872,7 +872,9 @@ static void intel_init_ppin(const struct cpuinfo_x86 *c) case 0x56: /* Broadwell Xeon D */ case 0x57: /* Knights Landing */ case 0x6a: /* Icelake X */ + case 0x6c: /* Icelake D */ case 0x85: /* Knights Mill */ + case 0x8f: /* Sapphire Rapids X */ if ( (c != &boot_cpu_data && !ppin_msr) || rdmsr_safe(MSR_PPIN_CTL, val) ) -- 2.30.2