From cc4a96ca5fb52ee085681dc5f8cae86b287b466e Mon Sep 17 00:00:00 2001 From: GNU Libc Maintainers Date: Sat, 2 Oct 2021 13:47:40 +0100 Subject: [PATCH] local-powerpc8xx-dcbz Gbp-Pq: Topic powerpc Gbp-Pq: Name local-powerpc8xx-dcbz.diff --- sysdeps/unix/sysv/linux/powerpc/dl-auxv.h | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/sysdeps/unix/sysv/linux/powerpc/dl-auxv.h b/sysdeps/unix/sysv/linux/powerpc/dl-auxv.h index be2189732..1327bbc85 100644 --- a/sysdeps/unix/sysv/linux/powerpc/dl-auxv.h +++ b/sysdeps/unix/sysv/linux/powerpc/dl-auxv.h @@ -23,8 +23,25 @@ int GLRO(dl_cache_line_size); #endif /* Scan the Aux Vector for the "Data Cache Block Size" entry and assign it - to dl_cache_line_size. */ -#define DL_PLATFORM_AUXV \ + to dl_cache_line_size. We have to detect 8xx processors, which + have buggy dcbz implementations that cannot report page faults + correctly. That requires reading SPR, which is a privileged + operation. Fortunately 2.2.18 and later emulates PowerPC mfspr + reads from the PVR register. */ +#ifndef __powerpc64__ + #define DL_PLATFORM_AUXV \ + case AT_DCACHEBSIZE: \ + { \ + unsigned pvr = 0; \ + asm ("mfspr %0, 287" : "=r" (pvr)); \ + if ((pvr & 0xffff0000) == 0x00500000) \ + break; \ + } \ + GLRO(dl_cache_line_size) = av->a_un.a_val; \ + break; +#else + #define DL_PLATFORM_AUXV \ case AT_DCACHEBSIZE: \ GLRO(dl_cache_line_size) = av->a_un.a_val; \ break; +#endif -- 2.30.2