From c99775d597fae9b8b8b27827b3d7845c49a2a0d7 Mon Sep 17 00:00:00 2001 From: Haozhong Zhang Date: Fri, 23 Feb 2018 10:59:31 +0100 Subject: [PATCH] VT-d: use two 32-bit writes to update DMAR fault address registers MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit The 64-bit DMAR fault address is composed of two 32 bits registers DMAR_FEADDR_REG and DMAR_FEUADDR_REG. According to VT-d spec: "Software is expected to access 32-bit registers as aligned doublewords", a hypervisor should use two 32-bit writes to DMAR_FEADDR_REG and DMAR_FEUADDR_REG separately in order to update a 64-bit fault address, rather than a 64-bit write to DMAR_FEADDR_REG. Note that when x2APIC is not enabled DMAR_FEUADDR_REG is reserved and it's not necessary to update it. Though I haven't seen any errors caused by such one 64-bit write on real machines, it's still better to follow the specification. Fixes: ae05fd3912b ("VT-d: use qword MMIO access for MSI address writes") Signed-off-by: Haozhong Zhang Reviewed-by: Roger Pau Monné Acked-by: Kevin Tian --- xen/drivers/passthrough/vtd/iommu.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/xen/drivers/passthrough/vtd/iommu.c b/xen/drivers/passthrough/vtd/iommu.c index daaed0abbd..08bce92d40 100644 --- a/xen/drivers/passthrough/vtd/iommu.c +++ b/xen/drivers/passthrough/vtd/iommu.c @@ -1105,7 +1105,13 @@ static void dma_msi_set_affinity(struct irq_desc *desc, const cpumask_t *mask) spin_lock_irqsave(&iommu->register_lock, flags); dmar_writel(iommu->reg, DMAR_FEDATA_REG, msg.data); - dmar_writeq(iommu->reg, DMAR_FEADDR_REG, msg.address); + dmar_writel(iommu->reg, DMAR_FEADDR_REG, msg.address_lo); + /* + * When x2APIC is not enabled, DMAR_FEUADDR_REG is reserved and + * it's not necessary to update it. + */ + if ( x2apic_enabled ) + dmar_writel(iommu->reg, DMAR_FEUADDR_REG, msg.address_hi); spin_unlock_irqrestore(&iommu->register_lock, flags); } -- 2.30.2