From c44dc590f89b02e89b464c6eb14bab07af7baeb1 Mon Sep 17 00:00:00 2001 From: Jan Beulich Date: Thu, 22 Mar 2018 10:36:55 +0100 Subject: [PATCH] x86emul: adjust_bnd() should check XCR0 Experimentally MPX instructions have been confirmed to behave as NOPs unless both related XCR0 bits are set to 1. By implication branches then also don't clear BNDn. Signed-off-by: Jan Beulich Reviewed-by: Andrew Cooper --- xen/arch/x86/x86_emulate/x86_emulate.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/x86_emulate/x86_emulate.c b/xen/arch/x86/x86_emulate/x86_emulate.c index bad5af4254..c4f34ca95c 100644 --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -2154,12 +2154,16 @@ static bool umip_active(struct x86_emulate_ctxt *ctxt, static void adjust_bnd(struct x86_emulate_ctxt *ctxt, const struct x86_emulate_ops *ops, enum vex_pfx pfx) { - uint64_t bndcfg; + uint64_t xcr0, bndcfg; int rc; if ( pfx == vex_f2 || !cpu_has_mpx || !vcpu_has_mpx() ) return; + if ( !ops->read_xcr || ops->read_xcr(0, &xcr0, ctxt) != X86EMUL_OKAY || + !(xcr0 & X86_XCR0_BNDREGS) || !(xcr0 & X86_XCR0_BNDCSR) ) + return; + if ( !mode_ring0() ) bndcfg = read_bndcfgu(); else if ( !ops->read_msr || -- 2.30.2