From b9f6395590e5cf1ee9339db592fa5dae933e857f Mon Sep 17 00:00:00 2001 From: Jan Beulich Date: Tue, 21 May 2019 08:21:45 +0200 Subject: [PATCH] x86/cpuid: adjust dependencies of post-SSE ISA extensions Move AESNI, PCLMULQDQ, and SHA to SSE2, as all of them act on vectors of integers, whereas plain SSE supports vectors of single precision floats only. This is in line with how e.g. binutils and gcc treat them. Signed-off-by: Jan Beulich Acked-by: Andrew Cooper --- xen/tools/gen-cpuid.py | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/xen/tools/gen-cpuid.py b/xen/tools/gen-cpuid.py index 6fbe129b3c..f8bd686852 100755 --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -196,11 +196,12 @@ def crunch_numbers(state): # instructions. Several futher instruction sets are built on core # %XMM support, without specific inter-dependencies. Additionally # AMD has a special mis-alignment sub-mode. - SSE: [SSE2, SSE3, SSSE3, SSE4A, MISALIGNSSE, - AESNI, PCLMULQDQ, SHA], + SSE: [SSE2, SSE3, SSSE3, SSE4A, MISALIGNSSE], - # SSE2 was re-specified as core instructions for 64bit. - SSE2: [LM], + # SSE2 was re-specified as core instructions for 64bit. Also ISA + # extensions dealing with vectors of integers are added here rather + # than to SSE. + SSE2: [LM, AESNI, PCLMULQDQ, SHA], # SSE4.1 explicitly depends on SSE3 and SSSE3 SSE3: [SSE4_1], -- 2.30.2