From b8428a858aba2200abe83afa1eb7c8115979c509 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Roger=20Pau=20Monn=C3=A9?= Date: Tue, 11 Jan 2022 11:42:49 +0100 Subject: [PATCH] x86/viridian: EOI MSR should always happen in affected vCPU context MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit The HV_X64_MSR_EOI wrmsr should always happen with the target vCPU as current, as there's no support for EOI'ing interrupts on a remote vCPU. While there also turn the unconditional assert at the top of the function into an error on non-debug builds. No functional change intended. Requested-by: Jan Beulich Signed-off-by: Roger Pau Monné Reviewed-by: Paul Durrant Reviewed-by: Jan Beulich --- xen/arch/x86/hvm/viridian/synic.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/hvm/viridian/synic.c b/xen/arch/x86/hvm/viridian/synic.c index 22e2df27e5..e18538c60a 100644 --- a/xen/arch/x86/hvm/viridian/synic.c +++ b/xen/arch/x86/hvm/viridian/synic.c @@ -79,11 +79,20 @@ int viridian_synic_wrmsr(struct vcpu *v, uint32_t idx, uint64_t val) struct viridian_vcpu *vv = v->arch.hvm.viridian; struct domain *d = v->domain; - ASSERT(v == current || !v->is_running); + if ( v != current && v->is_running ) + { + ASSERT_UNREACHABLE(); + return X86EMUL_EXCEPTION; + } switch ( idx ) { case HV_X64_MSR_EOI: + if ( v != current ) + { + ASSERT_UNREACHABLE(); + return X86EMUL_EXCEPTION; + } vlapic_EOI_set(vcpu_vlapic(v)); break; -- 2.30.2