From b5087a31efee7a4e34c958b88671ac6669501b09 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Roger=20Pau=20Monn=C3=A9?= Date: Tue, 3 Dec 2019 14:15:35 +0100 Subject: [PATCH] x86/tlbflush: do not toggle the PGE CR4 bit unless necessary MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit When PCID is not available Xen does a full tlbflush by toggling the PGE bit in CR4. This is not necessary if PGE is not enabled, since a flush can be performed by writing to CR3 in that case. Change the code in do_tlb_flush to only toggle the PGE bit in CR4 if it's already enabled, otherwise do the tlb flush by writing to CR3. This is relevant when running virtualized, since hypervisors don't usually trap accesses to CR3 when using hardware assisted paging, but do trap accesses to CR4 specially on AMD hardware, which makes such accesses much more expensive. Signed-off-by: Roger Pau Monné Reviewed-by: Jan Beulich --- xen/arch/x86/flushtlb.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/xen/arch/x86/flushtlb.c b/xen/arch/x86/flushtlb.c index c1ae0d9467..03f92c23dc 100644 --- a/xen/arch/x86/flushtlb.c +++ b/xen/arch/x86/flushtlb.c @@ -83,7 +83,7 @@ static void post_flush(u32 t) static void do_tlb_flush(void) { - unsigned long flags; + unsigned long flags, cr4; u32 t; /* This non-reentrant function is sometimes called in interrupt context. */ @@ -93,13 +93,13 @@ static void do_tlb_flush(void) if ( use_invpcid ) invpcid_flush_all(); - else + else if ( (cr4 = read_cr4()) & X86_CR4_PGE ) { - unsigned long cr4 = read_cr4(); - - write_cr4(cr4 ^ X86_CR4_PGE); + write_cr4(cr4 & ~X86_CR4_PGE); write_cr4(cr4); } + else + write_cr3(read_cr3()); post_flush(t); -- 2.30.2