From 92ba85ec925abeb25b7176d4963b3d7d4126e898 Mon Sep 17 00:00:00 2001 From: Boris Ostrovsky Date: Wed, 7 Mar 2012 07:30:30 +0000 Subject: [PATCH] x86: Use deep C states for off-lined CPUs Currently when a core is taken off-line it is placed in C1 state (unless MONITOR/MWAIT is used). This patch allows a core to go to deeper C states resulting in significantly higher power savings. Signed-off-by: Boris Ostrovsky Committed-by: Keir Fraser --- xen/arch/x86/acpi/cpu_idle.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c index a675867f24..75593d146a 100644 --- a/xen/arch/x86/acpi/cpu_idle.c +++ b/xen/arch/x86/acpi/cpu_idle.c @@ -566,6 +566,7 @@ static void acpi_dead_idle(void) { struct acpi_processor_power *power; struct acpi_processor_cx *cx; + struct cpuinfo_x86 *c = ¤t_cpu_data; if ( (power = processor_powers[smp_processor_id()]) == NULL ) goto default_halt; @@ -601,6 +602,23 @@ static void acpi_dead_idle(void) mb(); __mwait(cx->address, 0); } + } + else if ( c->x86_vendor == X86_VENDOR_AMD && + cx->entry_method == ACPI_CSTATE_EM_SYSIO ) + { + /* Intel prefers not to use SYSIO */ + + /* Avoid references to shared data after the cache flush */ + u32 address = cx->address; + u32 pmtmr_ioport_local = pmtmr_ioport; + + wbinvd(); + + while ( 1 ) + { + inb(address); + inl(pmtmr_ioport_local); + } } else if ( current_cpu_data.x86_vendor == X86_VENDOR_AMD && cx->entry_method == ACPI_CSTATE_EM_SYSIO ) -- 2.30.2