From 92b9dd5ddc50ea16e21a93980cf9101ca33b06f1 Mon Sep 17 00:00:00 2001
From: Andrzej Ratajewski <andrzej.ratajewski@intel.com>
Date: Tue, 7 Mar 2023 13:51:36 +0100
Subject: [PATCH] [PATCH 16/79] Fix mangling of opcodes from
 SPV_KHR_bit_instructions in SPV-IR (#1869)

Gbp-Pq: Name 0016-Fix-mangling-of-opcodes-from-SPV_KHR_bit_instruction.patch
---
 lib/SPIRV/SPIRVUtil.cpp                     |  3 +++
 test/transcoding/cl_khr_extended_bit_ops.cl | 20 ++++++++++++++------
 2 files changed, 17 insertions(+), 6 deletions(-)

diff --git a/lib/SPIRV/SPIRVUtil.cpp b/lib/SPIRV/SPIRVUtil.cpp
index 4889d7b..44c0384 100644
--- a/lib/SPIRV/SPIRVUtil.cpp
+++ b/lib/SPIRV/SPIRVUtil.cpp
@@ -2233,6 +2233,7 @@ public:
     case OpGroupNonUniformBallotFindMSB:
       addUnsignedArg(1);
       break;
+    case OpBitFieldSExtract:
     case OpGroupNonUniformBallotBitExtract:
       addUnsignedArg(1);
       addUnsignedArg(2);
@@ -2253,6 +2254,7 @@ public:
     case OpGroupNonUniformLogicalXor:
       addUnsignedArg(3);
       break;
+    case OpBitFieldInsert:
     case OpGroupNonUniformUMax:
     case OpGroupNonUniformUMin:
       addUnsignedArg(2);
@@ -2303,6 +2305,7 @@ public:
     case OpSubgroupAvcImeSetSingleReferenceINTEL:
       addUnsignedArg(1);
       break;
+    case OpBitFieldUExtract:
     case OpSubgroupAvcImeInitializeINTEL:
     case OpSubgroupAvcMceSetMotionVectorCostFunctionINTEL:
     case OpSubgroupAvcSicSetIntraLumaModeCostFunctionINTEL:
diff --git a/test/transcoding/cl_khr_extended_bit_ops.cl b/test/transcoding/cl_khr_extended_bit_ops.cl
index 3da301b..363d077 100644
--- a/test/transcoding/cl_khr_extended_bit_ops.cl
+++ b/test/transcoding/cl_khr_extended_bit_ops.cl
@@ -3,12 +3,15 @@
 // RUN: llvm-spirv %t.bc --spirv-ext=+SPV_KHR_bit_instructions -o %t.spv
 // RUN: llvm-spirv -r %t.spv -o %t.rev.bc
 // RUN: llvm-dis < %t.rev.bc | FileCheck %s --check-prefix=CHECK-LLVM
+// RUN: llvm-spirv -r --spirv-target-env=SPV-IR -emit-opaque-pointers %t.spv -o %t.rev.bc
+// RUN: llvm-dis < %t.rev.bc | FileCheck %s --check-prefix=CHECK-SPV-IR
 
 // CHECK-SPIRV: Capability BitInstructions
 // CHECK-SPIRV: Extension "SPV_KHR_bit_instructions"
 
 // CHECK-LLVM-LABEL: @testInsert
-// CHECK-LLVM: call spir_func <2 x i32> @_Z15bitfield_insertDv2_iS_jj
+// CHECK-LLVM: call spir_func <2 x i32> @_Z15bitfield_insertDv2_iS_jj(
+// CHECK-SPV-IR: call spir_func <2 x i32> @_Z22__spirv_BitFieldInsertDv2_iS_jj(
 // CHECK-SPIRV: Function
 // CHECK-SPIRV: FunctionParameter {{[0-9]+}} [[insbase:[0-9]+]]
 // CHECK-SPIRV: FunctionParameter {{[0-9]+}} [[insins:[0-9]+]]
@@ -18,8 +21,10 @@ kernel void testInsert(int2 b, int2 i, global int2 *res) {
 }
 
 // CHECK-LLVM-LABEL: @testExtractS
-// CHECK-LLVM: call spir_func i16 @_Z23bitfield_extract_signedsjj
-// CHECK-LLVM: call spir_func i16 @_Z23bitfield_extract_signedsjj
+// CHECK-LLVM: call spir_func i16 @_Z23bitfield_extract_signedsjj(
+// CHECK-LLVM: call spir_func i16 @_Z23bitfield_extract_signedsjj(
+// CHECK-SPV-IR: call spir_func i16 @_Z24__spirv_BitFieldSExtractsjj(
+// CHECK-SPV-IR: call spir_func i16 @_Z24__spirv_BitFieldSExtractsjj(
 // CHECK-SPIRV: Function
 // CHECK-SPIRV: FunctionParameter {{[0-9]+}} [[sextrbase:[0-9]+]]
 // CHECK-SPIRV: FunctionParameter {{[0-9]+}} [[sextrbaseu:[0-9]+]]
@@ -31,8 +36,10 @@ kernel void testExtractS(short b, ushort bu, global short *res) {
 }
 
 // CHECK-LLVM-LABEL: @testExtractU
-// CHECK-LLVM: call spir_func <8 x i8> @_Z25bitfield_extract_unsignedDv8_cjj
-// CHECK-LLVM: call spir_func <8 x i8> @_Z25bitfield_extract_unsignedDv8_cjj
+// CHECK-LLVM: call spir_func <8 x i8> @_Z25bitfield_extract_unsignedDv8_cjj(
+// CHECK-LLVM: call spir_func <8 x i8> @_Z25bitfield_extract_unsignedDv8_cjj(
+// CHECK-SPV-IR: call spir_func <8 x i8> @_Z24__spirv_BitFieldUExtractDv8_hjj(
+// CHECK-SPV-IR: call spir_func <8 x i8> @_Z24__spirv_BitFieldUExtractDv8_hjj(
 // CHECK-SPIRV: Function
 // CHECK-SPIRV: FunctionParameter {{[0-9]+}} [[uextrbase:[0-9]+]]
 // CHECK-SPIRV: FunctionParameter {{[0-9]+}} [[uextrbaseu:[0-9]+]]
@@ -44,7 +51,8 @@ kernel void testExtractU(char8 b, uchar8 bu, global uchar8 *res) {
 }
 
 // CHECK-LLVM-LABEL: @testBitReverse
-// CHECK-LLVM: call <4 x i64> @llvm.bitreverse.v4i64
+// CHECK-LLVM: call <4 x i64> @llvm.bitreverse.v4i64(
+// CHECK-SPV-IR: call <4 x i64> @llvm.bitreverse.v4i64(
 // CHECK-SPIRV: Function
 // CHECK-SPIRV: FunctionParameter {{[0-9]+}} [[revbase:[0-9]+]]
 // CHECK-SPIRV: BitReverse {{[0-9]+}} {{[0-9]+}} [[revbase]]
-- 
2.30.2