From 6fd56bc825e633470fb0807785cd32dbee8182a6 Mon Sep 17 00:00:00 2001 From: Haozhong Zhang Date: Wed, 8 Mar 2017 15:10:45 +0100 Subject: [PATCH] x86/mce: clear MSR_IA32_MCG_STATUS by writing 0 On Intel CPU, an attemp to write to MSR_IA32_MCG_STATUS with any non-zero value would result in #GP. This commit writes 0 on AMD CPU as well instead of just clearing MCIP bit, because all non-reserved bits of MSR_IA32_MCG_STATUS have been handled at this point. Signed-off-by: Haozhong Zhang Reviewed-by: Jan Beulich Reviewed-by: Boris Ostrovsky --- xen/arch/x86/cpu/mcheck/mce.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/x86/cpu/mcheck/mce.c b/xen/arch/x86/cpu/mcheck/mce.c index c4ffb27f60..35117f8c8f 100644 --- a/xen/arch/x86/cpu/mcheck/mce.c +++ b/xen/arch/x86/cpu/mcheck/mce.c @@ -535,7 +535,7 @@ void mcheck_cmn_handler(const struct cpu_user_regs *regs) gstatus = mca_rdmsr(MSR_IA32_MCG_STATUS); if ((gstatus & MCG_STATUS_MCIP) != 0) { mce_printk(MCE_CRITICAL, "MCE: Clear MCIP@ last step"); - mca_wrmsr(MSR_IA32_MCG_STATUS, gstatus & ~MCG_STATUS_MCIP); + mca_wrmsr(MSR_IA32_MCG_STATUS, 0); } mce_barrier_exit(&mce_trap_bar); -- 2.30.2