From 6bc54c0696c0f6f639598363d284c7188a9e20ae Mon Sep 17 00:00:00 2001 From: Andrew Cooper Date: Thu, 5 Mar 2020 11:38:13 +0100 Subject: [PATCH] x86/msr: Virtualise MSR_PLATFORM_ID properly This is an Intel-only, read-only MSR related to microcode loading. Expose it in similar circumstances as the PATCHLEVEL MSR. This should have been alongside c/s 013896cb8b2 "x86/msr: Fix handling of MSR_AMD_PATCHLEVEL/MSR_IA32_UCODE_REV" Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich master commit: 691265f96097d4fe3e46ff4267451d49b30143e6 master date: 2020-02-20 17:29:50 +0000 --- xen/arch/x86/msr.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index 35d99a98a1..ccb316c547 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -157,6 +157,13 @@ int guest_rdmsr(const struct vcpu *v, uint32_t msr, uint64_t *val) /* Not offered to guests. */ goto gp_fault; + case MSR_IA32_PLATFORM_ID: + if ( cp->x86_vendor != X86_VENDOR_INTEL || + boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ) + goto gp_fault; + rdmsrl(MSR_IA32_PLATFORM_ID, *val); + break; + case MSR_AMD_PATCHLEVEL: BUILD_BUG_ON(MSR_IA32_UCODE_REV != MSR_AMD_PATCHLEVEL); /* @@ -229,6 +236,7 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val) { uint64_t rsvd; + case MSR_IA32_PLATFORM_ID: case MSR_INTEL_CORE_THREAD_COUNT: case MSR_INTEL_PLATFORM_INFO: case MSR_ARCH_CAPABILITIES: -- 2.30.2