From 3a914ae3455a05a1b7bd992843b8922e4f94ff29 Mon Sep 17 00:00:00 2001 From: Julien Grall Date: Tue, 22 Apr 2014 14:41:14 +0100 Subject: [PATCH] xen/arm: debug-exynos4210: Remove early_uart_init The function early_uart_init contains specific initialization for the Arndale Board 5250. Usually U-boot as already setup the UART correctly (ie. clock, baud rate...) so we don't have to do again. Futhermore, this code won't work on new platform such as the Arndale Octa. Signed-off-by: Julien Grall Cc: HyonYoung Choi Cc: Meng Xu Acked-by: Ian Campbell --- xen/arch/arm/Rules.mk | 1 - xen/arch/arm/arm32/debug-exynos4210.inc | 32 ------------------------- 2 files changed, 33 deletions(-) diff --git a/xen/arch/arm/Rules.mk b/xen/arch/arm/Rules.mk index c551afbf47..8d5624b21c 100644 --- a/xen/arch/arm/Rules.mk +++ b/xen/arch/arm/Rules.mk @@ -53,7 +53,6 @@ EARLY_UART_BASE_ADDRESS := 0x1c090000 endif ifeq ($(CONFIG_EARLY_PRINTK), exynos5250) EARLY_PRINTK_INC := exynos4210 -EARLY_PRINTK_INIT_UART := y EARLY_PRINTK_BAUD := 115200 EARLY_UART_BASE_ADDRESS := 0x12c20000 endif diff --git a/xen/arch/arm/arm32/debug-exynos4210.inc b/xen/arch/arm/arm32/debug-exynos4210.inc index 39f2db360b..752942de0d 100644 --- a/xen/arch/arm/arm32/debug-exynos4210.inc +++ b/xen/arch/arm/arm32/debug-exynos4210.inc @@ -18,38 +18,6 @@ #include -/* Exynos 5 UART initialization - * rb: register which contains the UART base address - * rc: scratch register 1 - * rd: scratch register 2 */ -.macro early_uart_init rb rc rd - /* init clock */ - ldr \rc, =0x10020000 - /* select MPLL (800MHz) source clock */ - ldr \rd, [\rc, #0x250] - and \rd, \rd, #(~(0xf<<8)) - orr \rd, \rd, #(0x6<<8) - str \rd, [\rc, #0x250] - /* ratio 800/(7+1) */ - ldr \rd, [\rc, #0x558] - and \rd, \rd, #(~(0xf<<8)) - orr \rd, \rd, #(0x7<<8) - str \rd, [\rc, #0x558] - - mov \rc, #(100000000 / EARLY_PRINTK_BAUD % 16) - str \rc, [\rb, #UFRACVAL] /* -> UFRACVAL (Baud divisor fraction) */ - mov \rc, #(100000000 / EARLY_PRINTK_BAUD / 16 - 1) - str \rc, [\rb, #UBRDIV] /* -> UBRDIV (Baud divisor integer) */ - mov \rc, #3 /* 8n1 */ - str \rc, [\rb, #ULCON] /* -> (Line control) */ - ldr \rc, =UCON_TX_IRQ /* TX IRQMODE */ - str \rc, [\rb, #UCON] /* -> (Control Register) */ - mov \rc, #0x0 - str \rc, [\rb, #UFCON] /* disable FIFO */ - mov \rc, #0x0 - str \rc, [\rb, #UMCON] /* no auto flow control */ -.endm - /* Exynos 5 UART wait UART to be ready to transmit * rb: register which contains the UART base address * rc: scratch register */ -- 2.30.2