From 338db98dd8d2cf1a639951597880d7a2e7f3b3d6 Mon Sep 17 00:00:00 2001 From: George Dunlap Date: Thu, 8 Mar 2012 09:17:21 +0000 Subject: [PATCH] svm: Fake out the Bus Unit Config MSR on revF AMD CPUs Win2k8 x64 reads this MSR on revF chips, where it wasn't publically available; it uses a magic constant in %rdi as a password, which we don't have in rdmsr_safe(). Since we'll ignore the later writes, just use a plausible value here (the reset value from rev10h chips) if the real CPU didn't provide one. Signed-off-by: George Dunlap Committed-by: Keir Fraser --- xen/arch/x86/hvm/svm/svm.c | 12 ++++++++++++ xen/include/asm-x86/msr-index.h | 3 +++ 2 files changed, 15 insertions(+) diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index d89b3a2d6d..17b4a152aa 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -1505,6 +1505,18 @@ static int svm_msr_read_intercept(unsigned int msr, uint64_t *msr_content) if ( rdmsr_safe(msr, *msr_content) == 0 ) break; + if ( msr == MSR_F10_BU_CFG ) + { + /* Win2k8 x64 reads this MSR on revF chips, where it + * wasn't publically available; it uses a magic constant + * in %rdi as a password, which we don't have in + * rdmsr_safe(). Since we'll ignore the later writes, + * just use a plausible value here (the reset value from + * rev10h chips) if the real CPU didn't provide one. */ + *msr_content = 0x0000000010200020ull; + break; + } + goto gpf; } diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h index 4c773741e8..7d988258ec 100644 --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -209,6 +209,9 @@ #define MSR_F10_MC4_MISC2 0xc0000409 #define MSR_F10_MC4_MISC3 0xc000040A +/* AMD Family10h MMU control MSRs */ +#define MSR_F10_BU_CFG 0xc0011023 + /* Other AMD Fam10h MSRs */ #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 #define FAM10H_MMIO_CONF_ENABLE (1<<0) -- 2.30.2