From 2454fa428d0b0d1705b8395db7674426ebf182aa Mon Sep 17 00:00:00 2001 From: =?utf8?q?Roger=20Pau=20Monn=C3=A9?= Date: Mon, 7 Sep 2020 10:37:23 +0200 Subject: [PATCH] x86/vmx: handle writes to MISC_ENABLE MSR MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Such handling consist in checking that no bits have been changed from the read value, if that's the case silently drop the write, otherwise inject a fault. At least Windows guests will expect to write to the MISC_ENABLE MSR with the same value that's been read from it. Signed-off-by: Roger Pau Monné Acked-by: Andrew Cooper Reviewed-by: Kevin Tian --- xen/arch/x86/hvm/vmx/vmx.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index a0d58ffbe2..c4b40bf3cb 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -3163,7 +3163,7 @@ static int vmx_msr_write_intercept(unsigned int msr, uint64_t msr_content) switch ( msr ) { - uint64_t rsvd; + uint64_t rsvd, tmp; case MSR_IA32_SYSENTER_CS: __vmwrite(GUEST_SYSENTER_CS, msr_content); @@ -3301,6 +3301,17 @@ static int vmx_msr_write_intercept(unsigned int msr, uint64_t msr_content) /* None of these MSRs are writeable. */ goto gp_fault; + case MSR_IA32_MISC_ENABLE: + /* + * Silently drop writes that don't change the reported value: At least + * some Windows guests will expect to be able to write to MISC_ENABLE + * with the same value that's been read from it. + */ + if ( vmx_msr_read_intercept(msr, &tmp) != X86EMUL_OKAY || + tmp != msr_content ) + goto gp_fault; + break; + case MSR_P6_PERFCTR(0)...MSR_P6_PERFCTR(7): case MSR_P6_EVNTSEL(0)...MSR_P6_EVNTSEL(7): case MSR_CORE_PERF_FIXED_CTR0...MSR_CORE_PERF_FIXED_CTR2: -- 2.30.2