From 1448429664da9a3c33fc64cbbdde6508b86ecb2e Mon Sep 17 00:00:00 2001 From: Daniel De Graaf Date: Fri, 22 Jun 2012 13:44:54 +0200 Subject: [PATCH] x86/PCI: pass correct register value to XSM When attempting to use AMD's extension to access the extended PCI config space, only the low byte of the register number was being passed to XSM. Include the correct value of the register if this feature is enabled; otherwise, bits 24-30 of port cf8 are reserved, so disallow the invalid access. Signed-off-by: Daniel De Graaf Don't fail the permission check except when the MSR can't be read. Signed-off-by: Jan Beulich Acked-by: Keir Fraser Committed-by: Jan Beulich --- xen/arch/x86/traps.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index f0ef7626f8..767be86a18 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -1701,6 +1701,18 @@ static int pci_cfg_ok(struct domain *d, int write, int size) return 0; } start = d->arch.pci_cf8 & 0xFF; + /* AMD extended configuration space access? */ + if ( (d->arch.pci_cf8 & 0x0F000000) && + boot_cpu_data.x86_vendor == X86_VENDOR_AMD && + boot_cpu_data.x86 >= 0x10 && boot_cpu_data.x86 <= 0x17 ) + { + uint64_t msr_val; + + if ( rdmsr_safe(MSR_AMD64_NB_CFG, msr_val) ) + return 0; + if ( msr_val & (1ULL << AMD64_NB_CFG_CF8_EXT_ENABLE_BIT) ) + start |= (d->arch.pci_cf8 >> 16) & 0xF00; + } end = start + size - 1; if (xsm_pci_config_permission(d, machine_bdf, start, end, write)) return 0; -- 2.30.2