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(parent: ee41b5c) | patch
x86/Intel: insert Tiger Lake model numbers
authorJan Beulich <jbeulich@suse.com>
Tue, 22 Dec 2020 08:00:03 +0000 (09:00 +0100)
committerJan Beulich <jbeulich@suse.com>
Tue, 22 Dec 2020 08:00:03 +0000 (09:00 +0100)
commite93c3712d67098453760fd61c338cbf62dd08da1
tree8ceba12d62c3deb41e77e8259ec7479016bcc255tree | snapshot
parentee41b5c450032ae7f2531e18cd0a73bf5fb48803commit | diff
x86/Intel: insert Tiger Lake model numbers

Both match prior generation processors as far as LBR and C-state MSRs
go (SDM rev 073). The if_pschange_mc erratum, according to the spec
update, is not applicable.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
xen/arch/x86/acpi/cpu_idle.c diff | blob | history
xen/arch/x86/hvm/vmx/vmx.c diff | blob | history
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