Keir Fraser [Mon, 27 Oct 2008 13:29:35 +0000 (13:29 +0000)]
x86: highmem handling assistance hypercalls
While looking at the origin of very frequently executed hypercalls I
realized that the high page accessor functions in Linux would be good
candidates to handle in the hypervisor - clearing or copying to/from
a high page is a pretty frequent operation (provided there's enough
memory in the domain). While prior to the first submission I only
measured kernel builds (where the results are not hinting at a
meaningful improvement), I now found time to do a more specific
analysis: page clearing is being improved by about 20%, page copying
doesn't seem to significantly benefit (though that may be an effect of
the simplistic copy_page() implementation Xen currently uses) -
nevertheless I would think that if one function is supported by the
hypervisor, then the other should also be.
Keir Fraser [Mon, 27 Oct 2008 13:22:43 +0000 (13:22 +0000)]
x86: fix domain cleanup
The preemptable page type handling changes modified free_page_type()
behavior without adjusting the call site in relinquish_memory(): Any
type reference left pending when leaving hypercall handlers is
associated with a page reference, and when successful free_page_type()
decrements the type refcount - hence relinquish_memory() must now also
drop the page reference.
Also, the recursion avoidance during domain shutdown somehow (probably
by me when I merged the patch up to a newer snapshot) got screwed up:
The avoidance logic in mm.c should short circuit levels below the top
one currently being processed, rather than the top one itself.
Keir Fraser [Mon, 27 Oct 2008 13:20:52 +0000 (13:20 +0000)]
x86/powernow: fix machine shutdown
cpufreq_del_cpu() calls cpufreq_driver->exit() without checking
whether an exit() handler is present, and by adding an exit() handler
to powernow we can at once close the potential memory leak.
Keir Fraser [Mon, 27 Oct 2008 10:08:48 +0000 (10:08 +0000)]
x86: relax restrictions on reserved bits in L3 for 32on64 x86 guests
A 32on64 guest cannot copy an existing pinned L3 entry to use as a new
L3 because COMPAT_L3_DISALLOW_MASK contains bits which are added to L3
entries by adjust_guest_l3e (U/S & R/W) or by the hardware (A & D).
Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Keir Fraser [Thu, 23 Oct 2008 10:40:59 +0000 (11:40 +0100)]
x86, hvm: Move return-to-guest timer and interrupt cranking logic
outside of IRQ-safe context. This allows us to safely take
non-IRQ-safe spinlocks.
The drawback is that {vmx,svm}_intr_assist() now races new event
notifications delivered by IRQ or IPI. We close down this race by
having vcpu_kick() send a dummy softirq -- this gets picked up in
IRQ-sage context and will cause retry of *_intr_assist(). We avoid
delivering the softirq where possible by avoiding it when we are
running in the non-IRQ context of the VCPU to be kicked.
Keir Fraser [Wed, 22 Oct 2008 11:04:32 +0000 (12:04 +0100)]
Port HPET device model to vpt timer subsystem
The current hpet implementation runs a one-shot xen timer for each
hpet timer whenever the main counter is enabled regardless of whether
or not the individual hpet timers are enabled. When the timer fires,
if it is enabled the interrupt is routed to the guest. If the hpet
timer is periodic, a new one-shot timer is set, for NOW()+period.
There are a number of problems with this the most significant is guest
time drift. Windows does not read the hardware clock to verify time,
it depends on timer interrupts firing at the expected interval. The
existing implementation queues a new one-shot timer each time it fires
and does not allow for a difference between NOW() and the time the
timer was expected to fire, causing drift. Also there is
no allowance for lost ticks. This modification changes HPET to use the
Virtual Platform Timer (VPT) and, for periodic timers, to use periodic
timers. The VPT ensures an interrupt is delivered to the guest for
each period that elapses, plus, its use of xen periodic timers ensures
no drift.
Signed-off-by: Peter Johnston <peter.johnston@citrix.com>
Isaku Yamahata [Wed, 22 Oct 2008 02:38:22 +0000 (11:38 +0900)]
[IA64] fix compilation error of xen/common/spinlock.c
This patch fixes the error in the x86 tree.
> spinlock.c: In function _spin_lock_recursive:
> spinlock.c:59: error: dereferencing pointer to incomplete type
Keir Fraser [Tue, 21 Oct 2008 08:48:56 +0000 (09:48 +0100)]
Update cpufreq statistic protection
For struct pm_px, there are 3 pointer: pxpt, pt, trans_pt.
Partly free pointer 'pt' and 'trans_pt' will result in little memory
leak, and what is more, will result in protection issue when user
access px statistic info through libxc.
Keir Fraser [Tue, 21 Oct 2008 08:47:33 +0000 (09:47 +0100)]
x86: Adapt 32b guest os to 64b hypervisor platform_hypercall compatibility
Changeset 18552 (19b0a4f91712) move px transfer logic from
platform_hypercall.c to a common file to support both x86 and
ia64. However, it involves 32b guest os to 64b hypervisor (x86)
compatible issue. This patch fix the compatible issue, and make
set_px_pminfo() re-used by ia64 and x86 (32b guest os to 64b
hypervisor, and 64b guest os to 64b hypervisor).
Signed-off-by: Liu Jinsong <jinsong.liu@intel.com>
Keir Fraser [Mon, 20 Oct 2008 15:48:17 +0000 (16:48 +0100)]
Clean up spinlock operations and compile as first-class functions.
This follows modern Linux, since apparently outlining spinlock
operations does not slow down execution. The cleanups will also allow
more convenient addition of diagnostic code.
Keir Fraser [Mon, 20 Oct 2008 14:31:54 +0000 (15:31 +0100)]
vmx: avoid taking locks with irqs disabled
Shuffle the bits of the vmexit handler that run with EFLAGS.IF == 0 up
to the top. Otherwise we end up calling spin_lock() with interrupts
disabled, which can deadlock against the time-synchronization
rendezvous code.
Keir Fraser [Mon, 20 Oct 2008 14:22:58 +0000 (15:22 +0100)]
x86: add movnti emulation
Linux added the use of movnti for copying from user to kernel space in
certain cases, and as per reports we got this may happen with the
destination being in MMIO.
Keir Fraser [Mon, 20 Oct 2008 14:19:39 +0000 (15:19 +0100)]
VT-d: correct allocation failure checks
Checking the return value of map_domain_page() (and hence
map_vtd_domain_page()) against NULL is pointless, checking the return
value of alloc_domheap_page() (and thus alloc_pgtable_maddr()) is
mandatory, however.
Keir Fraser [Mon, 20 Oct 2008 14:17:24 +0000 (15:17 +0100)]
xend: fix setting vcpus > VCPUs_max
From reading xend code related to changing number of vcpus it appears
setting the number of vcpus to a value greater than VCPUs_max is not
allowed on a running domain. This restriction is not honored by
setVCpuCount() in XendDomainInfo.py. Attached patch makes
setVCpuCount() fail if vcpus > VCPUs_max and domain is running.
Also, I think the changes should be reflected in managed config of
running domain if in fact the domain is managed - so unconditionally
call managed_config_save().
BTW, the original code is rather confusing. Essentially the same
actions are taken regardless if self.info['VCPUs_max'] > vcpus, just
the order of invocation is changed. But this doesn't seem to matter
since self.info['VCPUs_live'] is not subsequently used.
Keir Fraser [Fri, 17 Oct 2008 11:00:25 +0000 (12:00 +0100)]
Enable PCI serial devices for console messages
The basic issue is that some PCI serial devices use a non-standard
crystal to control the baud rate divisor. This patch enhances the
`com' parameter to enable you to specify the crystal frequency used by
the serial device. Since this parameter already allows you to specify
I/O address and IRQ this is all that is needed to get a PCI serial
device to work. With this patch the `com' parameter is now defined
as:
comN=BBB[/CCC][,NPS[,III[,IRQ]]]
Where `CCC' is the crystal frequency. Note that if you specify 0 for
`IRQ' Xen will run the serial device in polled mode, obviating the
need for interrupts (an advantage since this is the only way I was
able to get my PCI serial device to work).
Keir Fraser [Thu, 16 Oct 2008 17:45:48 +0000 (18:45 +0100)]
NextRIPS support for forthcoming AMD processors
Future versions of AMD processors will support a feature called
NextRIPS or Next RIP Save. This feature causes the processor
to store the next sequential RIP of a guest in the VMCB on
most instruction interrupts. The hypervisor can use this
information to determine how much memory to read to determine
the intercepted instruction, modestly improving performance.
The following patch implements support for this feature.
Signed-off-by: Mark Langsdorf <mark.langsdorf@amd.com>
Keir Fraser [Thu, 16 Oct 2008 10:09:50 +0000 (11:09 +0100)]
xmalloc: use tlsf algorithm
This patch replaces the Xen xmalloc engine with tlsf, an allocation
engine that is both more space efficient and time-bounded, especially
for allocation sizes between PAGE_SIZE/2 and PAGE_SIZE.
The file xmalloc.c is deprecated but not yet deleted. A simple
changein common/Makefile will change back to the legacy xmalloc/xfree
if needed for testing.
Code adapted from Nitin Gupta's tlsf-kmod, rev 229, found here:
http://code.google.com/p/compcache/source/browse/trunk/sub-projects/allocat=
ors/tlsf-kmod
with description and performance details here:
http://code.google.com/p/compcache/wiki/TLSFAllocator
(new Xen code uses 4K=3DPAGE_SIZE for the region size)
For detailed info on tlsf, see:
http://rtportal.upv.es/rtmalloc/
Signed-off-by: Dan Magenheimer <dan.magenheimer@oracle.com> Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
Keir Fraser [Thu, 16 Oct 2008 08:50:18 +0000 (09:50 +0100)]
Enhance XenAPI for pvSCSI
Basically, I implemented XenAPI for pvSCSI according to the patch of
XenAPI document which I sent before. However, I renamed the class
name of virtual SCSI devices to "DSCSI".
Isaku Yamahata [Thu, 16 Oct 2008 02:33:05 +0000 (11:33 +0900)]
[IA64] rename struct viosapic_rte in order to share VTD code.
VTD code uses vioapic_redir_entry structure,
This patch lets viosapci.h use the same structure name and some fields.
That IA64 can use the same VTD code with ia32
Keir Fraser [Wed, 15 Oct 2008 14:57:20 +0000 (15:57 +0100)]
amd: fix CPUID mask option handling
c/s 18402 added command line options to AMD-specific code duplicating
ones already existing in Intel code. The generic command line parser
didn't support this scenario for integer options, however.
Additionally, the options added were using the same option string for
two different purposes.
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