From: Christian Gmeiner <cgmeiner@igalia.com>
Date: Fri, 18 Apr 2025 21:35:20 +0000 (+0200)
Subject: [PATCH 1/3] etnaviv: isa: Add txf instruction
X-Git-Tag: archive/raspbian/25.0.7-2+rpi1^2^2~1
X-Git-Url: https://dgit.raspbian.org/?a=commitdiff_plain;h=f19ca9bbb199e272a06f475a68334fa92acac6c6;p=mesa.git

[PATCH 1/3] etnaviv: isa: Add txf instruction

This instruction is used to implement texelfetch.

Blob generates such txf's for
dEQP-GLES3.functional.shaders.texture_functions.texelfetch.+

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34685>

Gbp-Pq: Name etnaviv-add-support-for-texelfetch.patch
---

diff --git a/src/etnaviv/isa/etnaviv.xml b/src/etnaviv/isa/etnaviv.xml
index 9893aab56..aa36a3b04 100644
--- a/src/etnaviv/isa/etnaviv.xml
+++ b/src/etnaviv/isa/etnaviv.xml
@@ -1350,6 +1350,11 @@ SPDX-License-Identifier: MIT
 	<pattern pos="80">1</pattern> <!-- OPCODE_BIT6 -->
 </bitset>
 
+<bitset name="txf" extends="#instruction-tex-src0-src1-src2">
+	<pattern low="0" high="5">001001</pattern> <!-- OPC -->
+	<pattern pos="80">1</pattern> <!-- OPCODE_BIT6 -->
+</bitset>
+
 <bitset name="imadlo0" extends="#instruction-alu-src0-src1-src2">
 	<pattern low="0" high="5">001100</pattern> <!-- OPC -->
 	<pattern pos="80">1</pattern> <!-- OPCODE_BIT6 -->
diff --git a/src/etnaviv/isa/tests/disasm.cpp b/src/etnaviv/isa/tests/disasm.cpp
index dc0a26a49..dddd83df6 100644
--- a/src/etnaviv/isa/tests/disasm.cpp
+++ b/src/etnaviv/isa/tests/disasm.cpp
@@ -165,6 +165,7 @@ INSTANTIATE_TEST_SUITE_P(Opcodes, DisasmTest,
       disasm_state{ {0x00801036, 0x15400804, 0x01540050, 0x00000002}, "clamp0_max        t0.x___, u0.yyyy, u0.zzzz, void\n"},
       disasm_state{ {0x0080103b, 0x00001804, 0x40000000, 0x00400028}, "iaddsat.s32       t0.x___, t1.xxxx, void, -t2.xxxx\n"},
       disasm_state{ {0x01001008, 0x15400804, 0xd00100c0, 0x00000007}, "imod.u16          t0._y__, t0.yyyy, 1, void\n"},
+      disasm_state{ {0x07811009, 0x15001f20, 0x01ff00c0, 0x78021008}, "txf               t1, tex0.xyzw, t1.xyyy, t1.wwww, 4352\n", FLAG_FAILING_ASM},
       disasm_state{ {0x0080103c, 0x00001804, 0x40000140, 0x00000000}, "imullo0.s32       t0.x___, t1.xxxx, t2.xxxx, void\n"},
       disasm_state{ {0x00801000, 0x00001804, 0x40010140, 0x00000000}, "imulhi0.s32       t0.x___, t1.xxxx, t2.xxxx, void\n"},
       disasm_state{ {0x00801004, 0x00201804, 0x40010040, 0x00000000}, "idiv0.s16         t0.x___, t1.xxxx, t0.xxxx, void\n"},
diff --git a/src/gallium/drivers/etnaviv/etnaviv_compiler_nir_emit.c b/src/gallium/drivers/etnaviv/etnaviv_compiler_nir_emit.c
index 08a5ab5fb..708f0788b 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_compiler_nir_emit.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_compiler_nir_emit.c
@@ -212,6 +212,10 @@ etna_emit_tex(struct etna_compile *c, nir_texop op, unsigned texid, unsigned dst
    case nir_texop_txb: inst.opcode = ISA_OPC_TEXLDB; break;
    case nir_texop_txd: inst.opcode = ISA_OPC_TEXLDD; break;
    case nir_texop_txl: inst.opcode = ISA_OPC_TEXLDL; break;
+   case nir_texop_txf:
+      inst.opcode = ISA_OPC_TXF;
+      inst.src[2] = etna_immediate_int(0x1100);
+      break;
    default:
       compile_error(c, "Unhandled NIR tex type: %d\n", op);
    }
diff --git a/src/gallium/drivers/etnaviv/etnaviv_nir_lower_texture.c b/src/gallium/drivers/etnaviv/etnaviv_nir_lower_texture.c
index d0462ead0..d20d175da 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_nir_lower_texture.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_nir_lower_texture.c
@@ -26,6 +26,28 @@ lower_txs(nir_builder *b, nir_instr *instr, UNUSED void *data)
    return true;
 }
 
+static bool
+legalize_txf_lod(nir_builder *b, nir_instr *instr, UNUSED void *data)
+{
+   if (instr->type != nir_instr_type_tex)
+      return false;
+
+   nir_tex_instr *tex = nir_instr_as_tex(instr);
+
+   if (tex->op != nir_texop_txf)
+      return false;
+
+   b->cursor = nir_before_instr(instr);
+
+   int lod_index = nir_tex_instr_src_index(tex, nir_tex_src_lod);
+   assert(lod_index >= 0);
+   nir_def *lod = tex->src[lod_index].src.ssa;
+
+   nir_src_rewrite(&tex->src[lod_index].src, nir_i2f32(b, lod));
+
+   return true;
+}
+
 bool
 etna_nir_lower_texture(nir_shader *s, struct etna_shader_key *key)
 {
@@ -48,5 +70,8 @@ etna_nir_lower_texture(nir_shader *s, struct etna_shader_key *key)
    NIR_PASS(progress, s, nir_shader_instructions_pass, lower_txs,
          nir_metadata_control_flow, NULL);
 
+   NIR_PASS(progress, s, nir_shader_instructions_pass, legalize_txf_lod,
+      nir_metadata_control_flow, NULL);
+
    return progress;
 }