From: Shanker Donthineni Date: Thu, 17 Mar 2016 12:46:58 +0000 (+0100) Subject: arm64: fix incorrect memory region size in TCR_EL2 X-Git-Tag: archive/raspbian/4.8.0-1+rpi1~1^2~1540 X-Git-Url: https://dgit.raspbian.org/?a=commitdiff_plain;h=eb6fe7a46997df408cda3e74038f7367fc1768af;p=xen.git arm64: fix incorrect memory region size in TCR_EL2 The maximum and minimum values for TxSZ depend on level of translation as per AArch64 Virtual Memory System Architecture. According to ARM specification DDI0487A_h (sec D4.2.2, page 1752), the minimum TxSZ value is 16. If TxSZ is programmed to a value smaller than 16 then it is IMPLEMENTATION DEFINED. This patch sets T0SZ to (64-48)bits since XEN uses all 4 levels to cover 48bit (256TB) virtual address instead of value zero. Signed-off-by: Shanker Donthineni Acked-by: Julien Grall --- diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index 19fa2bb3f7..946e2c93e9 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -342,8 +342,8 @@ skip_bss: * Top byte is used * PT walks use Inner-Shareable accesses, * PT walks are write-back, write-allocate in both cache levels, - * Full 64-bit address space goes through this table. */ - ldr x0, =(TCR_RES1|TCR_SH0_IS|TCR_ORGN0_WBWA|TCR_IRGN0_WBWA|TCR_T0SZ(0)) + * 48-bit virtual address space goes through this table. */ + ldr x0, =(TCR_RES1|TCR_SH0_IS|TCR_ORGN0_WBWA|TCR_IRGN0_WBWA|TCR_T0SZ(64-48)) /* ID_AA64MMFR0_EL1[3:0] (PARange) corresponds to TCR_EL2[18:16] (PS) */ mrs x1, ID_AA64MMFR0_EL1 bfi x0, x1, #16, #3