From: Jan Beulich Date: Tue, 22 Dec 2020 08:00:03 +0000 (+0100) Subject: x86/Intel: insert Tiger Lake model numbers X-Git-Tag: archive/raspbian/4.16.0+51-g0941d6cb-1+rpi1~2^2~42^2~1231 X-Git-Url: https://dgit.raspbian.org/?a=commitdiff_plain;h=e93c3712d67098453760fd61c338cbf62dd08da1;p=xen.git x86/Intel: insert Tiger Lake model numbers Both match prior generation processors as far as LBR and C-state MSRs go (SDM rev 073). The if_pschange_mc erratum, according to the spec update, is not applicable. Signed-off-by: Jan Beulich Acked-by: Andrew Cooper --- diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c index 27e0b52621..c092086b33 100644 --- a/xen/arch/x86/acpi/cpu_idle.c +++ b/xen/arch/x86/acpi/cpu_idle.c @@ -183,6 +183,9 @@ static void do_get_hw_residencies(void *arg) /* Ice Lake */ case 0x7D: case 0x7E: + /* Tiger Lake */ + case 0x8C: + case 0x8D: /* Kaby Lake */ case 0x8E: case 0x9E: diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 86b8916a5d..2d4475ee3d 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -2776,6 +2776,8 @@ static const struct lbr_info *last_branch_msr_get(void) case 0x7a: /* Ice Lake */ case 0x7d: case 0x7e: + /* Tiger Lake */ + case 0x8c: case 0x8d: /* Tremont */ case 0x86: /* Kaby Lake */