From: Keir Fraser Date: Fri, 30 Jul 2010 10:36:34 +0000 (+0100) Subject: x86: unmask CPUID levels on Intel CPUs X-Git-Tag: archive/raspbian/4.8.0-1+rpi1~1^2~11706 X-Git-Url: https://dgit.raspbian.org/?a=commitdiff_plain;h=d4a2c8df0ac4cc35e86971ff80d4c4e01d2fd15a;p=xen.git x86: unmask CPUID levels on Intel CPUs If the CPUID limit bit in MSR_IA32_MISC_ENABLE is set, clear it to make all CPUID information available. This is required for some features to work, such as MWAIT in cpuidle, get cpu topology, XSAVE, etc. Signed-off-by: Wei Gang --- diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c index 67a40beb42..8a5a7c89bd 100644 --- a/xen/arch/x86/cpu/intel.c +++ b/xen/arch/x86/cpu/intel.c @@ -90,6 +90,20 @@ void __devinit early_intel_workaround(struct cpuinfo_x86 *c) /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */ if (c->x86 == 15 && c->x86_cache_alignment == 64) c->x86_cache_alignment = 128; + + /* Unmask CPUID levels if masked: */ + if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { + u64 misc_enable; + + rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); + + if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) { + misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID; + wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable); + c->cpuid_level = cpuid_eax(0); + printk("revised cpuid_level = %d\n", c->cpuid_level); + } + } } /* diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h index 150e19154f..813531bd8e 100644 --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -324,6 +324,7 @@ #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1<<11) #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1<<12) #define MSR_IA32_MISC_ENABLE_MONITOR_ENABLE (1<<18) +#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1<<22) #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1<<23) /* Intel Model 6 */