From: Ben Hutchings <ben@decadent.org.uk>
Date: Wed, 31 May 2017 19:59:05 +0000 (+0100)
Subject: Revert "MIPS: Loongson-3: Select MIPS_L1_CACHE_SHIFT_6"
X-Git-Tag: archive/raspbian/4.15.4-1+rpi1~1^2^2^2^2^2^2^2^2^2^2^2~23
X-Git-Url: https://dgit.raspbian.org/?a=commitdiff_plain;h=c920893089f1ff2eba20439bdb84552c41a4bf23;p=linux.git

Revert "MIPS: Loongson-3: Select MIPS_L1_CACHE_SHIFT_6"

This reverts commit 07d8aabff4903065bb472df9b040b8688fdc75a2 which was
commit 17c99d9421695a0e0de18bf1e7091d859e20ec1d upstream.  This
changed L1_CACHE_SHIFT which is used for structure alignment in many
places, thus would break ABI.


Gbp-Pq: Topic debian
Gbp-Pq: Name revert-mips-loongson-3-select-mips_l1_cache_shift_6.patch
---

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 5e844f68e84..5a4f2eb9d0d 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1368,7 +1368,6 @@ config CPU_LOONGSON3
 	select WEAK_ORDERING
 	select WEAK_REORDERING_BEYOND_LLSC
 	select MIPS_PGD_C0_CONTEXT
-	select MIPS_L1_CACHE_SHIFT_6
 	select GPIOLIB
 	help
 		The Loongson 3 processor implements the MIPS64R2 instruction