From: Pu Wen <puwen@hygon.cn>
Date: Thu, 4 Apr 2019 13:47:54 +0000 (+0800)
Subject: x86/traps: Add Hygon Dhyana support
X-Git-Tag: archive/raspbian/4.14.0+80-gd101b417b7-1+rpi1^2~63^2~2104
X-Git-Url: https://dgit.raspbian.org/?a=commitdiff_plain;h=c6d427a617b3c5fd7ad716dc24e1352f7ffe024e;p=xen.git

x86/traps: Add Hygon Dhyana support

The Hygon Dhyana processor has the methold to get the last exception
source IP from MSR0000_01DD. So add support for it if the boot param
ler is true.

Signed-off-by: Pu Wen <puwen@hygon.cn>
Acked-by: Jan Beulich <jbeulich@suse.com>
---

diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index ba1053fa68..8097ef3bf5 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -1973,6 +1973,9 @@ static unsigned int calc_ler_msr(void)
             return MSR_IA32_LASTINTFROMIP;
         }
         break;
+
+    case X86_VENDOR_HYGON:
+        return MSR_IA32_LASTINTFROMIP;
     }
 
     return 0;