From: Peter Michael Green Date: Thu, 1 Mar 2018 16:36:29 +0000 (+0000) Subject: Manual merge of version 2.0-2+rpi1 and 2.1-1 to produce 2.1-1+rpi1 X-Git-Tag: archive/raspbian/2.1-1+rpi1~3 X-Git-Url: https://dgit.raspbian.org/?a=commitdiff_plain;h=be7340fc6b35e1e169e9bf193c8019be86181b54;p=ffcall.git Manual merge of version 2.0-2+rpi1 and 2.1-1 to produce 2.1-1+rpi1 --- be7340fc6b35e1e169e9bf193c8019be86181b54 diff --cc debian/changelog index f81fff5,908861e..bbdfdad --- a/debian/changelog +++ b/debian/changelog @@@ -1,10 -1,15 +1,24 @@@ - ffcall (2.0-2+rpi1) buster-staging; urgency=medium ++ffcall (2.1-1+rpi1) buster-staging; urgency=medium + ++ [changes brought forward from 2.0-2+rpi1 by Peter Michael Green at Thu, 07 Dec 2017 01:23:49 +0000] + * Replace movw/movt with ldr psuedo instruction. + * Mark binaries as armv6 not armv7 + * Disable testsuite, it fails on some of our buildboxes. + - -- Peter Michael Green Thu, 07 Dec 2017 01:23:49 +0000 ++ -- Raspbian forward porter Thu, 01 Mar 2018 16:23:45 +0000 ++ + ffcall (2.1-1) unstable; urgency=medium + + * New upstream release. + * Update Vcs-* fields for move to salsa. + * Drop fix-powerpcspe.patch, outdated, no longer works. + * Drop trampoline-mips64el.patch, applied upstream. + * No longer disable PIE on armhf, not needed anymore. + * Bump to debhelper compat level 11. + * Bump Standards-Version to 4.1.3. + * d/copyright: reflect upstream changes. + + -- Sébastien Villemot Sat, 17 Feb 2018 21:30:10 +0100 ffcall (2.0-2) unstable; urgency=medium diff --cc debian/patches/series index 701c76e,1038e07..ad6cb95 --- a/debian/patches/series +++ b/debian/patches/series @@@ -1,4 -1,1 +1,2 @@@ - fix-powerpcspe.patch mips-fpxx.patch - trampoline-mips64el.patch +raspbian.patch diff --cc vacall/vacall-armhf-macro.S index 031ff1c,c6628bf..4b9c617 --- a/vacall/vacall-armhf-macro.S +++ b/vacall/vacall-armhf-macro.S @@@ -1,5 -1,156 +1,156 @@@ #include "asm-arm.h" + #ifdef __PIC__ - .arch armv7-a ++ .arch armv6 + .eabi_attribute 28, 1 + .eabi_attribute 20, 1 + .eabi_attribute 21, 1 + .eabi_attribute 23, 3 + .eabi_attribute 24, 1 + .eabi_attribute 25, 1 + .eabi_attribute 26, 1 + .eabi_attribute 30, 2 + .eabi_attribute 34, 1 + .eabi_attribute 18, 4 + .text + .align 2 + .global C(vacall_receiver) + .syntax unified + .arm + .fpu vfpv3-d16 + .type vacall_receiver, %function + FUNBEGIN(vacall_receiver) + // args = 20, pretend = 16, frame = 176 + // frame_needed = 1, uses_anonymous_args = 0 + sub sp, sp, $16 + mov ip, $0 + push {r4, r5, r6, fp, lr} + add fp, sp, $16 + add lr, fp, $4 + sub sp, sp, $180 + ldr r4, L(31) + add r6, fp, $20 + vstr.32 s0, [fp, $-152] + stm lr, {r0, r1, r2, r3} + L(PIC0): + add r4, pc, r4 + vstr.32 s1, [fp, $-148] + sub r0, fp, $196 + str lr, [fp, $-164] + str ip, [fp, $-196] + vstr.32 s2, [fp, $-144] + str ip, [fp, $-160] + str r6, [fp, $-180] + vstr.32 s3, [fp, $-140] + ldr r5, L(31)+4 + vstr.32 s4, [fp, $-136] + vstr.32 s5, [fp, $-132] + vstr.32 s6, [fp, $-128] + vstr.32 s7, [fp, $-124] + vstr.32 s8, [fp, $-120] + vstr.32 s9, [fp, $-116] + vstr.32 s10, [fp, $-112] + vstr.32 s11, [fp, $-108] + vstr.32 s12, [fp, $-104] + vstr.32 s13, [fp, $-100] + vstr.32 s14, [fp, $-96] + vstr.32 s15, [fp, $-92] + vstr.64 d0, [fp, $-84] + vstr.64 d1, [fp, $-76] + vstr.64 d2, [fp, $-68] + vstr.64 d3, [fp, $-60] + vstr.64 d4, [fp, $-52] + vstr.64 d5, [fp, $-44] + vstr.64 d6, [fp, $-36] + str ip, [fp, $-156] + str ip, [fp, $-176] + vstr.64 d7, [fp, $-28] + strb ip, [fp, $-172] + ldr r3, [r4, r5] + ldr r3, [r3] + blx r3 + ldrb r3, [fp, $-172] // zero_extendqisi2 + cmp r3, $0 + beq L(1) + cmp r3, $1 + beq L(25) + cmp r3, $2 + ldrsbeq r0, [fp, $-188] + beq L(1) + cmp r3, $3 + beq L(25) + cmp r3, $4 + ldrsheq r0, [fp, $-188] + beq L(1) + cmp r3, $5 + ldrheq r0, [fp, $-188] + beq L(1) + cmp r3, $6 + beq L(27) + cmp r3, $7 + beq L(27) + cmp r3, $8 + beq L(27) + cmp r3, $9 + beq L(27) + sub r2, r3, $10 + cmp r2, $1 + bls L(29) + cmp r3, $12 + vldreq.32 s0, [fp, $-188] + beq L(1) + cmp r3, $13 + vldreq.64 d0, [fp, $-188] + beq L(1) + cmp r3, $14 + beq L(27) + cmp r3, $15 + bne L(1) + ldr r3, [fp, $-196] + tst r3, $1024 + beq L(1) + ldr r3, [fp, $-168] + cmp r3, $1 + beq L(30) + cmp r3, $2 + ldr r3, [fp, $-176] + ldrheq r0, [r3] + ldrne r0, [r3] + L(1): + sub sp, fp, $16 + // sp needed + pop {r4, r5, r6, fp, lr} + add sp, sp, $16 + bx lr + L(25): + ldrb r0, [fp, $-188] // zero_extendqisi2 + sub sp, fp, $16 + // sp needed + pop {r4, r5, r6, fp, lr} + add sp, sp, $16 + bx lr + L(27): + ldr r0, [fp, $-188] + sub sp, fp, $16 + // sp needed + pop {r4, r5, r6, fp, lr} + add sp, sp, $16 + bx lr + L(29): + ldr r0, [fp, $-188] + ldr r1, [fp, $-184] + b L(1) + L(30): + ldr r3, [fp, $-176] + ldrb r0, [r3] // zero_extendqisi2 + b L(1) + L(32): + .align 2 + L(31): + .word _GLOBAL_OFFSET_TABLE_-(L(PIC0)+8) + .word C(vacall_function)(GOT) + FUNEND(vacall_receiver) + #else - .arch armv7-a + .arch armv6 .eabi_attribute 28, 1 .eabi_attribute 20, 1 .eabi_attribute 21, 1