From: BjoernSch <mail@bjoern-schrader.de>
Date: Sat, 6 Aug 2016 10:53:23 +0000 (+0200)
Subject: Fixed delay for I2C and SPI
X-Git-Tag: archive/raspbian/1.68-2+rpi1~77^2~4
X-Git-Url: https://dgit.raspbian.org/?a=commitdiff_plain;h=bcc77be5fbb411313a88b559da4da8b44294f2a4;p=pigpio.git

Fixed delay for I2C and SPI

Fixed delay for I2C - gone wrong in c91dbb5
Fixed delay for SPI, limited Software-SPI Speed to 250kbps, more is
possible but jitter makes the pulses too short without additional delay.
---

diff --git a/pigpio.c b/pigpio.c
index 3ae2a52..9a37053 100644
--- a/pigpio.c
+++ b/pigpio.c
@@ -10044,7 +10044,7 @@ int bbI2COpen(unsigned SDA, unsigned SCL, unsigned baud)
    wfRx[SDA].I.started = 0;
    wfRx[SDA].I.SDA = SDA;
    wfRx[SDA].I.SCL = SCL;
-   wfRx[SDA].I.delay = (500000 / baud) - 1;
+   wfRx[SDA].I.delay = 500000 / baud;
    wfRx[SDA].I.SDAMode = gpioGetMode(SDA);
    wfRx[SDA].I.SCLMode = gpioGetMode(SCL);
 
@@ -10109,7 +10109,7 @@ int bbSPIOpen(unsigned CS, unsigned MISO, unsigned MOSI, unsigned SCLK, unsigned
    wfRx[CS].S.MOSI = MOSI;
    wfRx[CS].S.CS = CS;
    wfRx[CS].S.SCLK = SCLK;
-   wfRx[CS].S.delay = 500000 / baud;
+   wfRx[CS].S.delay = (500000 / baud) - 1;
    wfRx[CS].S.spiFlags = spiFlags;
    wfRx[CS].S.MISOMode = gpioGetMode(MISO);
    wfRx[CS].S.MOSIMode = gpioGetMode(MOSI);
diff --git a/pigpio.h b/pigpio.h
index bdc3a9a..b82932e 100644
--- a/pigpio.h
+++ b/pigpio.h
@@ -597,7 +597,7 @@ typedef void *(gpioThreadFunc_t) (void *);
 #define PI_BB_I2C_MAX_BAUD 500000
 
 #define PI_BB_SPI_MIN_BAUD     50
-#define PI_BB_SPI_MAX_BAUD 500000
+#define PI_BB_SPI_MAX_BAUD 250000
 
 #define PI_BB_SER_MIN_BAUD     50
 #define PI_BB_SER_MAX_BAUD 250000
@@ -2640,7 +2640,7 @@ for the hardware SPI ports.
  MISO: 0-31
  MOSI: 0-31
  SCLK: 0-31
-baud: 50-500000
+baud: 50-250000
 spiFlags: see below
 . .
 spiFlags consists of the least significant 22 bits.
@@ -2662,6 +2662,12 @@ Mode POL PHA
 
 p0 is 0 if CEx is active low (default) and 1 for active high.
 
+T is 1 if the least significant bit is transmitted on MOSI first, the
+default (0) shifts the most significant bit out first.
+
+R is 1 if the least significant bit is received on MISO first, the
+default (0) receives the most significant bit first.
+
 The other bits in flags should be set to zero.
 
 Returns 0 if OK, otherwise PI_BAD_USER_GPIO, PI_BAD_SPI_BAUD, or