From: Stefano Stabellini Date: Tue, 5 Feb 2019 21:38:53 +0000 (-0800) Subject: xen/arm: gic-v2: deactivate interrupts during initialization X-Git-Tag: archive/raspbian/4.11.3+24-g14b62ab3e5-1+rpi1^2~55^2~76 X-Git-Url: https://dgit.raspbian.org/?a=commitdiff_plain;h=b52bcda6f53376031a94d86bc85fea8ef1b37a31;p=xen.git xen/arm: gic-v2: deactivate interrupts during initialization Interrupts could be ACTIVE at boot. Make sure to deactivate them during initialization. Signed-off-by: Stefano Stabellini Reviewed-by: Julien Grall CC: julien.grall@arm.com CC: peng.fan@nxp.com CC: jgross@suse.com (cherry picked from commit b4df73de493954c44f240f78779c9bd3782e1572) --- diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index d01b9c6aab..2cc86658a8 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -379,7 +379,10 @@ static void __init gicv2_dist_init(void) /* Disable all global interrupts */ for ( i = 32; i < nr_lines; i += 32 ) + { writel_gicd(~0x0, GICD_ICENABLER + (i / 32) * 4); + writel_gicd(~0x0, GICD_ICACTIVER + (i / 32) * 4); + } /* Turn on the distributor */ writel_gicd(GICD_CTL_ENABLE, GICD_CTLR); @@ -394,6 +397,7 @@ static void gicv2_cpu_init(void) /* The first 32 interrupts (PPI and SGI) are banked per-cpu, so * even though they are controlled with GICD registers, they must * be set up here with the other per-cpu state. */ + writel_gicd(0xffffffff, GICD_ICACTIVER); /* Diactivate PPIs and SGIs */ writel_gicd(0xffff0000, GICD_ICENABLER); /* Disable all PPI */ writel_gicd(0x0000ffff, GICD_ISENABLER); /* Enable all SGI */