From: Andrew Cooper Date: Fri, 27 Mar 2020 12:02:09 +0000 (+0000) Subject: x86/ucode: Drop the sanity check for interrupts being disabled X-Git-Tag: archive/raspbian/4.14.0+80-gd101b417b7-1+rpi1^2~63^2~483 X-Git-Url: https://dgit.raspbian.org/?a=commitdiff_plain;h=ac71d99c6aebfbeb321b32ba84125ac6f2699a41;p=xen.git x86/ucode: Drop the sanity check for interrupts being disabled Of the substantial number of things which can go wrong during microcode load, this is not one. Loading occurs entirely within the boundary of a single WRMSR instruction. Its certainly not a BUG()-worthy condition. Xen has legitimate reasons to not want interrupts enabled at this point, but that is to do with organising the system rendezvous. As these are private low level helpers invoked only from the microcode core logic, forgo the check entirely. While dropping system.h, clean up the processor.h include which was an oversight in the previous header cleanup. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- diff --git a/xen/arch/x86/cpu/microcode/amd.c b/xen/arch/x86/cpu/microcode/amd.c index 96b80ff960..9efc03c810 100644 --- a/xen/arch/x86/cpu/microcode/amd.c +++ b/xen/arch/x86/cpu/microcode/amd.c @@ -20,8 +20,6 @@ #include #include -#include -#include #include "private.h" @@ -232,8 +230,6 @@ static int apply_microcode(const struct microcode_patch *patch) hdr = patch->mc_amd->mpb; - BUG_ON(local_irq_is_enabled()); - hw_err = wrmsr_safe(MSR_AMD_PATCHLOADER, (unsigned long)hdr); /* get patch id after patching */ diff --git a/xen/arch/x86/cpu/microcode/intel.c b/xen/arch/x86/cpu/microcode/intel.c index 78455aa0ae..49c46cd146 100644 --- a/xen/arch/x86/cpu/microcode/intel.c +++ b/xen/arch/x86/cpu/microcode/intel.c @@ -25,8 +25,6 @@ #include #include -#include -#include #include "private.h" @@ -283,8 +281,6 @@ static int apply_microcode(const struct microcode_patch *patch) mc_intel = patch->mc_intel; - BUG_ON(local_irq_is_enabled()); - /* write microcode via MSR 0x79 */ wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc_intel->bits); wrmsrl(MSR_IA32_UCODE_REV, 0x0ULL);