From: Chris Wilson Date: Mon, 25 Jan 2021 22:02:47 +0000 (+0000) Subject: drm/i915/gt: Flush before changing register state X-Git-Tag: archive/raspbian/5.10.19-1+rpi1^2~38 X-Git-Url: https://dgit.raspbian.org/?a=commitdiff_plain;h=ac2a27ce167b3f92b7974b8b566ccf1f986df63f;p=linux.git drm/i915/gt: Flush before changing register state Origin: https://git.kernel.org/linus/d5109f739c9f14a3bda249cb48b16de1065932f0 Flush; invalidate; change registers; invalidate; flush. Will this finally work on every device? Or will Baytrail complain again? On the positive side, we immediately see the benefit of having hsw-gt1 in CI. Fixes: ace44e13e577 ("drm/i915/gt: Clear CACHE_MODE prior to clearing residuals") Testcase: igt/gem_render_tiled_blits # hsw-gt1 Signed-off-by: Chris Wilson Cc: Mika Kuoppala Cc: Akeem G Abodunrin Acked-by: Mika Kuoppala Link: https://patchwork.freedesktop.org/patch/msgid/20210125220247.31701-1-chris@chris-wilson.co.uk (cherry picked from commit d30bbd62b1bfd9e0a33c3583c5a9e5d66f60cbd7) Signed-off-by: Rodrigo Vivi Gbp-Pq: Topic bugfix/x86 Gbp-Pq: Name drm-i915-gt-Flush-before-changing-register-state.patch --- diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c index c50b18dd67b..e53b409012c 100644 --- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c +++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c @@ -393,6 +393,7 @@ static void emit_batch(struct i915_vma * const vma, desc_count); /* Reset inherited context registers */ + gen7_emit_pipeline_flush(&cmds); gen7_emit_pipeline_invalidate(&cmds); batch_add(&cmds, MI_LOAD_REGISTER_IMM(2)); batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_0_GEN7));