From: GNU Libc Maintainers <debian-glibc@lists.debian.org>
Date: Sun, 10 Jul 2022 20:29:34 +0000 (+0100)
Subject: local-powerpc8xx-dcbz
X-Git-Tag: archive/raspbian/2.33-8+rpi1^2~30
X-Git-Url: https://dgit.raspbian.org/?a=commitdiff_plain;h=a3090fb88665cf195d33df6b7471cec19ede227c;p=glibc.git

local-powerpc8xx-dcbz


Gbp-Pq: Topic powerpc
Gbp-Pq: Name local-powerpc8xx-dcbz.diff
---

diff --git a/sysdeps/unix/sysv/linux/powerpc/dl-auxv.h b/sysdeps/unix/sysv/linux/powerpc/dl-auxv.h
index 36ba0f3e9..1c612db5e 100644
--- a/sysdeps/unix/sysv/linux/powerpc/dl-auxv.h
+++ b/sysdeps/unix/sysv/linux/powerpc/dl-auxv.h
@@ -23,8 +23,25 @@ int GLRO(dl_cache_line_size);
 #endif
 
 /* Scan the Aux Vector for the "Data Cache Block Size" entry and assign it
-   to dl_cache_line_size.  */
-#define DL_PLATFORM_AUXV						      \
+   to dl_cache_line_size. We have to detect 8xx processors, which
+   have buggy dcbz implementations that cannot report page faults
+   correctly.  That requires reading SPR, which is a privileged
+   operation.  Fortunately 2.2.18 and later emulates PowerPC mfspr
+   reads from the PVR register.  */
+#ifndef __powerpc64__
+ #define DL_PLATFORM_AUXV						      \
+      case AT_DCACHEBSIZE:						      \
+	{								      \
+	  unsigned pvr = 0;						      \
+	  asm ("mfspr %0, 287" : "=r" (pvr));				      \
+	  if ((pvr & 0xffff0000) == 0x00500000)				      \
+	    break;							      \
+	}								      \
+	GLRO(dl_cache_line_size) = av->a_un.a_val;			      \
+ 	break;
+#else
+ #define DL_PLATFORM_AUXV						      \
       case AT_DCACHEBSIZE:						      \
 	GLRO(dl_cache_line_size) = av->a_un.a_val;			      \
 	break;
+#endif