From: Keir Fraser Date: Sat, 8 Jan 2011 10:48:46 +0000 (+0000) Subject: Update AMD CPU feature flags 0x80000001:ECX for Xen Hypervisor X-Git-Tag: archive/raspbian/4.8.0-1+rpi1~1^2~10959 X-Git-Url: https://dgit.raspbian.org/?a=commitdiff_plain;h=9dee0481309a521fa6b2e464e37a8579851a2acb;p=xen.git Update AMD CPU feature flags 0x80000001:ECX for Xen Hypervisor This patch syncs-up AMD CPU feature flags 0x80000001:ECX with the latest Linux kernel. Several new features are added. Some of existing features' names are changed as well. Signed-off-by: Wei Huang --- diff --git a/xen/arch/x86/cpu/mcheck/amd_nonfatal.c b/xen/arch/x86/cpu/mcheck/amd_nonfatal.c index 4815253639..73e0a0f7e3 100644 --- a/xen/arch/x86/cpu/mcheck/amd_nonfatal.c +++ b/xen/arch/x86/cpu/mcheck/amd_nonfatal.c @@ -212,7 +212,7 @@ void amd_nonfatal_mcheck_init(struct cpuinfo_x86 *c) /* The threshold bitfields in MSR_IA32_MC4_MISC has * been introduced along with the SVME feature bit. */ - if (variable_period && cpu_has(c, X86_FEATURE_SVME)) { + if (variable_period && cpu_has(c, X86_FEATURE_SVM)) { uint64_t value; /* hw threshold registers present */ diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index 9e10a43109..968beedb42 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -919,7 +919,7 @@ struct hvm_function_table * __init start_svm(void) { bool_t printed = 0; - if ( !test_bit(X86_FEATURE_SVME, &boot_cpu_data.x86_capability) ) + if ( !test_bit(X86_FEATURE_SVM, &boot_cpu_data.x86_capability) ) return NULL; if ( svm_cpu_up() ) diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index 3da6f8278c..f7d8f69c9c 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -795,9 +795,9 @@ static void pv_cpuid(struct cpu_user_regs *regs) __clear_bit(X86_FEATURE_PAGE1GB % 32, &d); __clear_bit(X86_FEATURE_RDTSCP % 32, &d); - __clear_bit(X86_FEATURE_SVME % 32, &c); + __clear_bit(X86_FEATURE_SVM % 32, &c); if ( !cpu_has_apic ) - __clear_bit(X86_FEATURE_EXTAPICSPACE % 32, &c); + __clear_bit(X86_FEATURE_EXTAPIC % 32, &c); __clear_bit(X86_FEATURE_OSVW % 32, &c); __clear_bit(X86_FEATURE_IBS % 32, &c); __clear_bit(X86_FEATURE_SKINIT % 32, &c); diff --git a/xen/include/asm-x86/amd.h b/xen/include/asm-x86/amd.h index 9868a2f2ff..d7fb1a5b53 100644 --- a/xen/include/asm-x86/amd.h +++ b/xen/include/asm-x86/amd.h @@ -63,8 +63,8 @@ __bit(X86_FEATURE_CX16)) #define AMD_FEATURES_K8_REV_F_EDX AMD_FEATURES_K8_REV_E_EDX #define AMD_EXTFEATURES_K8_REV_F_ECX (AMD_EXTFEATURES_K8_REV_E_ECX |\ - __bit(X86_FEATURE_SVME) | __bit(X86_FEATURE_EXTAPICSPACE) | \ - __bit(X86_FEATURE_ALTMOVCR)) + __bit(X86_FEATURE_SVM) | __bit(X86_FEATURE_EXTAPIC) | \ + __bit(X86_FEATURE_CR8_LEGACY)) #define AMD_EXTFEATURES_K8_REV_F_EDX (AMD_EXTFEATURES_K8_REV_E_EDX |\ __bit(X86_FEATURE_RDTSCP)) @@ -72,7 +72,7 @@ #define AMD_FEATURES_K8_REV_G_ECX AMD_FEATURES_K8_REV_F_ECX #define AMD_FEATURES_K8_REV_G_EDX AMD_FEATURES_K8_REV_F_EDX #define AMD_EXTFEATURES_K8_REV_G_ECX (AMD_EXTFEATURES_K8_REV_F_ECX |\ - __bit(X86_FEATURE_3DNOWPF)) + __bit(X86_FEATURE_3DNOWPREFETCH)) #define AMD_EXTFEATURES_K8_REV_G_EDX AMD_EXTFEATURES_K8_REV_F_EDX /* Family 10h, Revision B */ diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h index e12785e891..8d9b49d610 100644 --- a/xen/include/asm-x86/cpufeature.h +++ b/xen/include/asm-x86/cpufeature.h @@ -118,20 +118,25 @@ #define X86_FEATURE_PMM_EN (5*32+ 13) /* PMM enabled */ /* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */ -#define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */ -#define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */ -#define X86_FEATURE_SVME (6*32+ 2) /* Secure Virtual Machine */ -#define X86_FEATURE_EXTAPICSPACE (6*32+ 3) /* Extended APIC space */ -#define X86_FEATURE_ALTMOVCR (6*32+ 4) /* LOCK MOV CR accesses CR+8 */ -#define X86_FEATURE_ABM (6*32+ 5) /* Advanced Bit Manipulation */ -#define X86_FEATURE_SSE4A (6*32+ 6) /* AMD Streaming SIMD Extensions-4a */ -#define X86_FEATURE_MISALIGNSSE (6*32+ 7) /* Misaligned SSE Access */ -#define X86_FEATURE_3DNOWPF (6*32+ 8) /* 3DNow! Prefetch */ -#define X86_FEATURE_OSVW (6*32+ 9) /* OS Visible Workaround */ -#define X86_FEATURE_IBS (6*32+ 10) /* Instruction Based Sampling */ -#define X86_FEATURE_SSE5 (6*32+ 11) /* AMD Streaming SIMD Extensions-5 */ -#define X86_FEATURE_SKINIT (6*32+ 12) /* SKINIT, STGI/CLGI, DEV */ -#define X86_FEATURE_WDT (6*32+ 13) /* Watchdog Timer */ +#define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */ +#define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */ +#define X86_FEATURE_SVM (6*32+ 2) /* Secure virtual machine */ +#define X86_FEATURE_EXTAPIC (6*32+ 3) /* Extended APIC space */ +#define X86_FEATURE_CR8_LEGACY (6*32+ 4) /* CR8 in 32-bit mode */ +#define X86_FEATURE_ABM (6*32+ 5) /* Advanced bit manipulation */ +#define X86_FEATURE_SSE4A (6*32+ 6) /* SSE-4A */ +#define X86_FEATURE_MISALIGNSSE (6*32+ 7) /* Misaligned SSE mode */ +#define X86_FEATURE_3DNOWPREFETCH (6*32+ 8) /* 3DNow prefetch instructions */ +#define X86_FEATURE_OSVW (6*32+ 9) /* OS Visible Workaround */ +#define X86_FEATURE_IBS (6*32+10) /* Instruction Based Sampling */ +#define X86_FEATURE_XOP (6*32+11) /* extended AVX instructions */ +#define X86_FEATURE_SKINIT (6*32+12) /* SKINIT/STGI instructions */ +#define X86_FEATURE_WDT (6*32+13) /* Watchdog timer */ +#define X86_FEATURE_LWP (6*32+15) /* Light Weight Profiling */ +#define X86_FEATURE_FMA4 (6*32+16) /* 4 operands MAC instructions */ +#define X86_FEATURE_NODEID_MSR (6*32+19) /* NodeId MSR */ +#define X86_FEATURE_TBM (6*32+21) /* trailing bit manipulations */ +#define X86_FEATURE_TOPOEXT (6*32+22) /* topology extensions CPUID leafs */ /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */ #define X86_FEATURE_FSGSBASE (7*32+ 0) /* {RD,WR}{FS,GS}BASE instructions */