From: Wei Huang <wei.huang2@amd.com>
Date: Sat, 28 May 2011 07:58:08 +0000 (+0100)
Subject: HVM/SVM: enable tsc scaling ratio for SVM
X-Git-Tag: archive/raspbian/4.8.0-1+rpi1~1^2~10263
X-Git-Url: https://dgit.raspbian.org/?a=commitdiff_plain;h=9405f63305fcda58fde390c38fb53db3a44963b0;p=xen.git

HVM/SVM: enable tsc scaling ratio for SVM

Future AMD CPUs support TSC scaling. It allows guests to have a
different TSC frequency from host system using this formula: guest_tsc
= host_tsc * tsc_ratio + vmcb_offset. The tsc_ratio is a 64bit MSR
contains a fixed-point number in 8.32 format (8 bits for integer part
and 32bits for fractional part). For instance 0x00000003_80000000
means tsc_ratio=3.5.

This patch enables TSC scaling ratio for SVM. With it, guest VMs don't
need take #VMEXIT to calculate a translated TSC value when it is
running under TSC emulation mode. This can substancially reduce the
rdtsc overhead.

Signed-off-by: Wei Huang <wei.huang2@amd.com>
---

diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c
index 9b9e0753c4..65a60ce714 100644
--- a/xen/arch/x86/hvm/svm/svm.c
+++ b/xen/arch/x86/hvm/svm/svm.c
@@ -640,8 +640,23 @@ static void svm_set_tsc_offset(struct vcpu *v, u64 offset)
     struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
     struct vmcb_struct *n1vmcb, *n2vmcb;
     uint64_t n2_tsc_offset = 0;
+    struct domain *d = v->domain;
+
+    if ( !nestedhvm_enabled(d) ) {
+        /* Re-adjust the offset value when TSC_RATIO is available */
+        if ( cpu_has_tsc_ratio && d->arch.vtsc )
+        {
+            uint64_t host_tsc, guest_tsc;
+
+            rdtscll(host_tsc);
+            guest_tsc = hvm_get_guest_tsc(v);
+            
+            /* calculate hi,lo parts in 64bits to prevent overflow */
+            offset = (((host_tsc >> 32) * d->arch.tsc_khz / cpu_khz) << 32) +
+                     (host_tsc & 0xffffffffULL) * d->arch.tsc_khz / cpu_khz;
+            offset = guest_tsc - offset;
+        }
 
-    if ( !nestedhvm_enabled(v->domain) ) {
         vmcb_set_tsc_offset(vmcb, offset);
         return;
     }
@@ -749,6 +764,19 @@ static int svm_update_lwp_cfg(struct vcpu *v, uint64_t msr_content)
     return 0;
 }
 
+static inline void svm_tsc_ratio_save(struct vcpu *v)
+{
+    /* Other vcpus might not have vtsc enabled. So disable TSC_RATIO here. */
+    if ( cpu_has_tsc_ratio && v->domain->arch.vtsc )
+        wrmsrl(MSR_AMD64_TSC_RATIO, DEFAULT_TSC_RATIO);
+}
+
+static inline void svm_tsc_ratio_load(struct vcpu *v)
+{
+    if ( cpu_has_tsc_ratio && v->domain->arch.vtsc ) 
+        wrmsrl(MSR_AMD64_TSC_RATIO, vcpu_tsc_ratio(v));
+}
+
 static void svm_ctxt_switch_from(struct vcpu *v)
 {
     int cpu = smp_processor_id();
@@ -758,6 +786,7 @@ static void svm_ctxt_switch_from(struct vcpu *v)
     svm_save_dr(v);
     vpmu_save(v);
     svm_lwp_save(v);
+    svm_tsc_ratio_save(v);
 
     svm_sync_vmcb(v);
     svm_vmload(per_cpu(root_vmcb, cpu));
@@ -802,6 +831,7 @@ static void svm_ctxt_switch_to(struct vcpu *v)
     vmcb->cleanbits.bytes = 0;
     vpmu_load(v);
     svm_lwp_load(v);
+    svm_tsc_ratio_load(v);
 
     if ( cpu_has_rdtscp )
         wrmsrl(MSR_TSC_AUX, hvm_msr_tsc_aux(v));
diff --git a/xen/arch/x86/hvm/svm/vmcb.c b/xen/arch/x86/hvm/svm/vmcb.c
index c26c760044..e604df9296 100644
--- a/xen/arch/x86/hvm/svm/vmcb.c
+++ b/xen/arch/x86/hvm/svm/vmcb.c
@@ -128,7 +128,9 @@ static int construct_vmcb(struct vcpu *v)
 
     /* TSC. */
     vmcb->_tsc_offset = 0;
-    if ( v->domain->arch.vtsc )
+
+    /* Don't need to intercept RDTSC if CPU supports TSC rate scaling */
+    if ( v->domain->arch.vtsc && !cpu_has_tsc_ratio )
     {
         vmcb->_general1_intercepts |= GENERAL1_INTERCEPT_RDTSC;
         vmcb->_general2_intercepts |= GENERAL2_INTERCEPT_RDTSCP;
diff --git a/xen/include/asm-x86/hvm/svm/svm.h b/xen/include/asm-x86/hvm/svm/svm.h
index 53f6ed5188..52b05e1ad3 100644
--- a/xen/include/asm-x86/hvm/svm/svm.h
+++ b/xen/include/asm-x86/hvm/svm/svm.h
@@ -87,7 +87,15 @@ extern u32 svm_feature_flags;
 #define cpu_has_svm_cleanbits cpu_has_svm_feature(SVM_FEATURE_VMCBCLEAN)
 #define cpu_has_svm_decode    cpu_has_svm_feature(SVM_FEATURE_DECODEASSISTS)
 #define cpu_has_pause_filter  cpu_has_svm_feature(SVM_FEATURE_PAUSEFILTER)
+#define cpu_has_tsc_ratio     cpu_has_svm_feature(SVM_FEATURE_TSCRATEMSR)
 
 #define SVM_PAUSEFILTER_INIT    3000
 
+/* TSC rate */
+#define DEFAULT_TSC_RATIO       0x0000000100000000ULL
+#define TSC_RATIO_RSVD_BITS     0xffffff0000000000ULL
+#define TSC_RATIO(g_khz, h_khz) ( (((u64)(g_khz)<<32)/(u64)(h_khz)) & \
+                                  ~TSC_RATIO_RSVD_BITS )
+#define vcpu_tsc_ratio(v)       TSC_RATIO((v)->domain->arch.tsc_khz, cpu_khz)
+
 #endif /* __ASM_X86_HVM_SVM_H__ */
diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index 8560fb3d63..f2e066c946 100644
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -266,6 +266,9 @@
 #define MSR_AMD_PATCHLEVEL		0x0000008b
 #define MSR_AMD_PATCHLOADER		0xc0010020
 
+/* AMD TSC RATE MSR */
+#define MSR_AMD64_TSC_RATIO		0xc0000104
+
 /* AMD Lightweight Profiling MSRs */
 #define MSR_AMD64_LWP_CFG		0xc0000105
 #define MSR_AMD64_LWP_CBADDR		0xc0000106