From: Bertrand Marquis Date: Thu, 17 Dec 2020 15:38:06 +0000 (+0000) Subject: xen/arm: Add handler for cp15 ID registers X-Git-Tag: archive/raspbian/4.16.0+51-g0941d6cb-1+rpi1~2^2~42^2~1216 X-Git-Url: https://dgit.raspbian.org/?a=commitdiff_plain;h=8f81064a07c64952931eafdd9a9a3017ed6ffd26;p=xen.git xen/arm: Add handler for cp15 ID registers Add support for emulation of cp15 based ID registers (on arm32 or when running a 32bit guest on arm64). The handlers are returning the values stored in the guest_cpuinfo structure for known registers and RAZ for all reserved registers. In the current status the MVFR registers are no supported. Signed-off-by: Bertrand Marquis [Stefano: fix code style] Signed-off-by: Stefano Stabellini Reviewed-by: Stefano Stabellini --- diff --git a/xen/arch/arm/vcpreg.c b/xen/arch/arm/vcpreg.c index cdc91cdf5b..cbab95b37a 100644 --- a/xen/arch/arm/vcpreg.c +++ b/xen/arch/arm/vcpreg.c @@ -155,6 +155,24 @@ TVM_REG32(CONTEXTIDR, CONTEXTIDR_EL1) break; \ } +/* Macro to generate easily case for ID co-processor emulation */ +#define GENERATE_TID3_INFO(reg, field, offset) \ + case HSR_CPREG32(reg): \ + { \ + return handle_ro_read_val(regs, regidx, cp32.read, hsr, 1, \ + guest_cpuinfo.field.bits[offset]);\ + } + +/* helper to define cases for all registers for one CRm value */ +#define HSR_CPREG32_TID3_CASES(REG) case HSR_CPREG32(p15,0,c0,REG,0): \ + case HSR_CPREG32(p15,0,c0,REG,1): \ + case HSR_CPREG32(p15,0,c0,REG,2): \ + case HSR_CPREG32(p15,0,c0,REG,3): \ + case HSR_CPREG32(p15,0,c0,REG,4): \ + case HSR_CPREG32(p15,0,c0,REG,5): \ + case HSR_CPREG32(p15,0,c0,REG,6): \ + case HSR_CPREG32(p15,0,c0,REG,7) + void do_cp15_32(struct cpu_user_regs *regs, const union hsr hsr) { const struct hsr_cp32 cp32 = hsr.cp32; @@ -286,6 +304,53 @@ void do_cp15_32(struct cpu_user_regs *regs, const union hsr hsr) */ return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); + /* + * HCR_EL2.TID3 + * + * This is trapping most Identification registers used by a guest + * to identify the processor features + */ + GENERATE_TID3_INFO(ID_PFR0, pfr32, 0) + GENERATE_TID3_INFO(ID_PFR1, pfr32, 1) + GENERATE_TID3_INFO(ID_PFR2, pfr32, 2) + GENERATE_TID3_INFO(ID_DFR0, dbg32, 0) + GENERATE_TID3_INFO(ID_DFR1, dbg32, 1) + GENERATE_TID3_INFO(ID_AFR0, aux32, 0) + GENERATE_TID3_INFO(ID_MMFR0, mm32, 0) + GENERATE_TID3_INFO(ID_MMFR1, mm32, 1) + GENERATE_TID3_INFO(ID_MMFR2, mm32, 2) + GENERATE_TID3_INFO(ID_MMFR3, mm32, 3) + GENERATE_TID3_INFO(ID_MMFR4, mm32, 4) + GENERATE_TID3_INFO(ID_MMFR5, mm32, 5) + GENERATE_TID3_INFO(ID_ISAR0, isa32, 0) + GENERATE_TID3_INFO(ID_ISAR1, isa32, 1) + GENERATE_TID3_INFO(ID_ISAR2, isa32, 2) + GENERATE_TID3_INFO(ID_ISAR3, isa32, 3) + GENERATE_TID3_INFO(ID_ISAR4, isa32, 4) + GENERATE_TID3_INFO(ID_ISAR5, isa32, 5) + GENERATE_TID3_INFO(ID_ISAR6, isa32, 6) + /* MVFR registers are in cp10 not cp15 */ + + /* + * Those cases are catching all Reserved registers trapped by TID3 which + * currently have no assignment. + * HCR.TID3 is trapping all registers in the group 3: + * coproc == p15, opc1 == 0, CRn == c0, CRm == {c2-c7}, opc2 == {0-7}. + * Those registers are defined as being RO in the Arm Architecture + * Reference manual Armv8 (Chapter D12.3.2 of issue F.c) so handle them + * as Read-only read as zero. + */ + case HSR_CPREG32(p15,0,c0,c3,0): + case HSR_CPREG32(p15,0,c0,c3,1): + case HSR_CPREG32(p15,0,c0,c3,2): + case HSR_CPREG32(p15,0,c0,c3,3): + case HSR_CPREG32(p15,0,c0,c3,7): + HSR_CPREG32_TID3_CASES(c4): + HSR_CPREG32_TID3_CASES(c5): + HSR_CPREG32_TID3_CASES(c6): + HSR_CPREG32_TID3_CASES(c7): + return handle_ro_raz(regs, regidx, cp32.read, hsr, 1); + /* * HCR_EL2.TIDCP *