From: Julien Grall Date: Mon, 16 Feb 2015 14:50:43 +0000 (+0000) Subject: xen/arm: vgic-v3: Correctly handle GICD_CTLR X-Git-Tag: archive/raspbian/4.8.0-1+rpi1~1^2~3745 X-Git-Url: https://dgit.raspbian.org/?a=commitdiff_plain;h=8d91d64e24b0248db44e394cdeabd6a6f68c8cb2;p=xen.git xen/arm: vgic-v3: Correctly handle GICD_CTLR As backward GICv2 compatibility is not supported in the vGICv3 driver, the bit ARE_NS is RAO/WI. Furthermore, when ARE_NS is set, the guest can only modify EnableGrp1A. At same time take the vgic_lock to write into domain.arch.vgic.ctrl. It was already taken during read. Signed-off-by: Julien Grall Acked-by: Ian Campbell --- diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index e0a7d5bd88..911519982a 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -45,6 +45,12 @@ #define GICV3_GICR_PIDR2 GICV3_GICD_PIDR2 #define GICV3_GICR_PIDR4 GICV3_GICD_PIDR4 +/* + * GICD_CTLR default value: + * - No GICv2 compatibility => ARE = 1 + */ +#define VGICD_CTLR_DEFAULT (GICD_CTLR_ARE_NS) + static struct vcpu *vgic_v3_irouter_to_vcpu(struct vcpu *v, uint64_t irouter) { irouter &= ~(GICD_IROUTER_SPI_MODE_ANY); @@ -838,8 +844,15 @@ static int vgic_v3_distr_mmio_write(struct vcpu *v, mmio_info_t *info) { case GICD_CTLR: if ( dabt.size != DABT_WORD ) goto bad_width; - /* Ignore all but the enable bit */ - v->domain->arch.vgic.ctlr = (*r) & GICD_CTL_ENABLE; + + vgic_lock(v); + /* Only EnableGrp1A can be changed */ + if ( *r & GICD_CTLR_ENABLE_G1A ) + v->domain->arch.vgic.ctlr |= GICD_CTLR_ENABLE_G1A; + else + v->domain->arch.vgic.ctlr &= ~GICD_CTLR_ENABLE_G1A; + vgic_unlock(v); + return 1; case GICD_TYPER: /* RO -- write ignored */ @@ -1100,6 +1113,8 @@ static int vgic_v3_domain_init(struct domain *d) register_mmio_handler(d, &vgic_rdistr_mmio_handler, d->arch.vgic.rbase[i], d->arch.vgic.rbase_size[i]); + d->arch.vgic.ctlr = VGICD_CTLR_DEFAULT; + return 0; }