From: Keir Fraser <keir.fraser@citrix.com>
Date: Mon, 13 Oct 2008 09:08:36 +0000 (+0100)
Subject: xend: fixup the Secondary Bus Reset.
X-Git-Tag: archive/raspbian/4.8.0-1+rpi1~1^2~14085
X-Git-Url: https://dgit.raspbian.org/?a=commitdiff_plain;h=7e3496ba25a44050452a0dae131a437e7fa93c80;p=xen.git

xend: fixup the Secondary Bus Reset.

Use the read-modify-write operation.
Change the wrong 'I' to a correct 'H'.

Signed-off-by: Dexuan Cui <dexuan.cui@intel.com>
---

diff --git a/tools/python/xen/util/pci.py b/tools/python/xen/util/pci.py
index 85bc0fc555..03309969f7 100644
--- a/tools/python/xen/util/pci.py
+++ b/tools/python/xen/util/pci.py
@@ -476,15 +476,16 @@ class PciDevice:
         parent_path = sysfs_mnt + SYSFS_PCI_DEVS_PATH + '/' + \
             target_bus + SYSFS_PCI_DEV_CONFIG_PATH
         fd = os.open(parent_path, os.O_RDWR)
-        # Save state of bridge control register - restore after reset
         os.lseek(fd, PCI_CB_BRIDGE_CONTROL, 0)
         br_cntl = (struct.unpack('H', os.read(fd, 2)))[0]
         # Assert Secondary Bus Reset
         os.lseek(fd, PCI_CB_BRIDGE_CONTROL, 0)
-        os.write(fd, struct.pack('I', PCI_BRIDGE_CTL_BUS_RESET))
+        br_cntl |= PCI_BRIDGE_CTL_BUS_RESET
+        os.write(fd, struct.pack('H', br_cntl))
         time.sleep(0.200)
         # De-assert Secondary Bus Reset
         os.lseek(fd, PCI_CB_BRIDGE_CONTROL, 0)
+        br_cntl &= ~PCI_BRIDGE_CTL_BUS_RESET
         os.write(fd, struct.pack('H', br_cntl))
         time.sleep(0.200)
         os.close(fd)