From: Haozhong Zhang <haozhong.zhang@intel.com>
Date: Wed, 8 Mar 2017 14:10:45 +0000 (+0100)
Subject: x86/mce: clear MSR_IA32_MCG_STATUS by writing 0
X-Git-Tag: archive/raspbian/4.11.1-1+rpi1~1^2~66^2~2541
X-Git-Url: https://dgit.raspbian.org/?a=commitdiff_plain;h=6fd56bc825e633470fb0807785cd32dbee8182a6;p=xen.git

x86/mce: clear MSR_IA32_MCG_STATUS by writing 0

On Intel CPU, an attemp to write to MSR_IA32_MCG_STATUS with any
non-zero value would result in #GP.

This commit writes 0 on AMD CPU as well instead of just clearing MCIP
bit, because all non-reserved bits of MSR_IA32_MCG_STATUS have been
handled at this point.

Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
---

diff --git a/xen/arch/x86/cpu/mcheck/mce.c b/xen/arch/x86/cpu/mcheck/mce.c
index c4ffb27f60..35117f8c8f 100644
--- a/xen/arch/x86/cpu/mcheck/mce.c
+++ b/xen/arch/x86/cpu/mcheck/mce.c
@@ -535,7 +535,7 @@ void mcheck_cmn_handler(const struct cpu_user_regs *regs)
     gstatus = mca_rdmsr(MSR_IA32_MCG_STATUS);
     if ((gstatus & MCG_STATUS_MCIP) != 0) {
         mce_printk(MCE_CRITICAL, "MCE: Clear MCIP@ last step");
-        mca_wrmsr(MSR_IA32_MCG_STATUS, gstatus & ~MCG_STATUS_MCIP);
+        mca_wrmsr(MSR_IA32_MCG_STATUS, 0);
     }
     mce_barrier_exit(&mce_trap_bar);