From: Jan Beulich Date: Thu, 15 Mar 2018 11:44:24 +0000 (+0100) Subject: x86: ignore guest microcode loading attempts X-Git-Tag: archive/raspbian/4.11.1-1+rpi1~1^2~66^2~402 X-Git-Url: https://dgit.raspbian.org/?a=commitdiff_plain;h=59c0983e10d70ea2368085271b75fb007811fe52;p=xen.git x86: ignore guest microcode loading attempts The respective MSRs are write-only, and hence attempts by guests to write to these are - as of 1f1d183d49 ("x86/HVM: don't give the wrong impression of WRMSR succeeding") no longer ignored. Restore original behavior for the two affected MSRs. Signed-off-by: Jan Beulich Reviewed-by: Andrew Cooper --- diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index 8ae3b4e616..369b4754ce 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -147,6 +147,8 @@ int guest_rdmsr(const struct vcpu *v, uint32_t msr, uint64_t *val) switch ( msr ) { + case MSR_AMD_PATCHLOADER: + case MSR_IA32_UCODE_WRITE: case MSR_PRED_CMD: /* Write-only */ goto gp_fault; @@ -200,6 +202,28 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val) /* Read-only */ goto gp_fault; + case MSR_AMD_PATCHLOADER: + /* + * See note on MSR_IA32_UCODE_WRITE below, which may or may not apply + * to AMD CPUs as well (at least the architectural/CPUID part does). + */ + if ( is_pv_domain(d) || + d->arch.cpuid->x86_vendor != X86_VENDOR_AMD ) + goto gp_fault; + break; + + case MSR_IA32_UCODE_WRITE: + /* + * Some versions of Windows at least on certain hardware try to load + * microcode before setting up an IDT. Therefore we must not inject #GP + * for such attempts. Also the MSR is architectural and not qualified + * by any CPUID bit. + */ + if ( is_pv_domain(d) || + d->arch.cpuid->x86_vendor != X86_VENDOR_INTEL ) + goto gp_fault; + break; + case MSR_SPEC_CTRL: if ( !cp->feat.ibrsb ) goto gp_fault; /* MSR available? */