From: David Vrabel <david.vrabel@citrix.com>
Date: Mon, 23 Jun 2014 17:57:01 +0000 (+0100)
Subject: tools/mce: add more MCE types to xen-mceinj
X-Git-Tag: archive/raspbian/4.8.0-1+rpi1~1^2~4755
X-Git-Url: https://dgit.raspbian.org/?a=commitdiff_plain;h=4b3b9d3e1922177cc1a5a5218c11dc4e18e3ebc0;p=xen.git

tools/mce: add more MCE types to xen-mceinj

Add a non-fatal MCE for AMD CPUs.

Add a fatal (PCC set) MCE for Intel CPUs.

Signed-off-by: David Vrabel <david.vrabel@citrix.com>
Acked-by: Christoph Egger <chegger@amazon.de>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
---

diff --git a/tools/tests/mce-test/tools/xen-mceinj.c b/tools/tests/mce-test/tools/xen-mceinj.c
index 1f872a5096..8ad045f66a 100644
--- a/tools/tests/mce-test/tools/xen-mceinj.c
+++ b/tools/tests/mce-test/tools/xen-mceinj.c
@@ -93,6 +93,22 @@ static struct mce_info mce_table[] = {
         .mci_misc = 0x86ull,
         .cmci = true,
     },
+    /* AMD L1 instruction cache data or tag parity. */
+    {
+        .description = "AMD L1 icache parity",
+        .mcg_stat = 0x5,
+        .bank = 1,
+        .mci_stat = 0x9400000000000151ull,
+        .mci_misc = 0x86ull,
+    },
+    /* LLC (Last Level Cache) EWB (Explicit Write Back) SRAO MCE */
+    {
+        .description = "MCE_SRAO_MEM (Fatal)",
+        .mcg_stat = 0x5,
+        .bank = 7,
+        .mci_stat = 0xBF2000008000017Aull,
+        .mci_misc = 0x86ull,
+    },
 };
 #define MCE_TABLE_SIZE (sizeof(mce_table)/sizeof(mce_table[0]))