From: James Clarke <jrtc27@jrtc27.com>
Date: Thu, 7 Dec 2017 20:32:44 +0000 (+0000)
Subject: powerpc/lib/sstep: Fix building for powerpcspe
X-Git-Tag: archive/raspbian/4.18.10-2+rpi1^2~82
X-Git-Url: https://dgit.raspbian.org/?a=commitdiff_plain;h=4a74ef85f21a3085fda6ed5d2dc7e5115e2f47dd;p=linux.git

powerpc/lib/sstep: Fix building for powerpcspe

On powerpcspe, ptesync is not a recognised instruction and so fails to
assemble. We don't expect to have to emulate an lwsync or a ptesync on a
32-bit kernel, so just ifdef them out, and catch any unexpected barrier
types.

Fixes: 3cdfcbfd32b9 ("powerpc: Change analyse_instr so it doesn't modify *regs")
Signed-off-by: James Clarke <jrtc27@jrtc27.com>

Gbp-Pq: Topic bugfix/powerpc
Gbp-Pq: Name powerpc-lib-sstep-fix-building-for-powerpcspe.patch
---

diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index d81568f783e..abdaf465727 100644
--- a/arch/powerpc/lib/sstep.c
+++ b/arch/powerpc/lib/sstep.c
@@ -2681,12 +2681,16 @@ void emulate_update_regs(struct pt_regs *regs, struct instruction_op *op)
 		case BARRIER_EIEIO:
 			eieio();
 			break;
+#ifdef __powerpc64__
 		case BARRIER_LWSYNC:
 			asm volatile("lwsync" : : : "memory");
 			break;
 		case BARRIER_PTESYNC:
 			asm volatile("ptesync" : : : "memory");
 			break;
+#endif
+		default:
+			WARN_ON_ONCE(1);
 		}
 		break;