From: Jan Beulich Date: Fri, 23 Aug 2013 07:23:24 +0000 (+0200) Subject: x86: correct public header's documentation of PAT MSR settings X-Git-Tag: archive/raspbian/4.8.0-1+rpi1~1^2~6468 X-Git-Url: https://dgit.raspbian.org/?a=commitdiff_plain;h=3829655bd3ad2b1150bd94955fc6988dec6b98f2;p=xen.git x86: correct public header's documentation of PAT MSR settings The first (PAT6) column was wrong across the board, and the column for PAT7 was missing altogether. Signed-off-by: Jan Beulich Acked-by: Keir Fraser --- diff --git a/xen/include/public/xen.h b/xen/include/public/xen.h index 2a409701fb..b50bd050ba 100644 --- a/xen/include/public/xen.h +++ b/xen/include/public/xen.h @@ -277,15 +277,15 @@ DEFINE_XEN_GUEST_HANDLE(xen_ulong_t); * refer to Intel SDM 10.12. The PAT allows to set the caching attributes of * pages instead of using MTRRs. * - * The PAT MSR is as follow (it is a 64-bit value, each entry is 8 bits): - * PAT4 PAT0 - * +---+----+----+----+-----+----+----+ - * WC | WC | WB | UC | UC- | WC | WB | <= Linux - * +---+----+----+----+-----+----+----+ - * WC | WT | WB | UC | UC- | WT | WB | <= BIOS (default when machine boots) - * +---+----+----+----+-----+----+----+ - * WC | WP | WC | UC | UC- | WT | WB | <= Xen - * +---+----+----+----+-----+----+----+ + * The PAT MSR is as follows (it is a 64-bit value, each entry is 8 bits): + * PAT4 PAT0 + * +-----+-----+----+----+----+-----+----+----+ + * | UC | UC- | WC | WB | UC | UC- | WC | WB | <= Linux + * +-----+-----+----+----+----+-----+----+----+ + * | UC | UC- | WT | WB | UC | UC- | WT | WB | <= BIOS (default when machine boots) + * +-----+-----+----+----+----+-----+----+----+ + * | rsv | rsv | WP | WC | UC | UC- | WT | WB | <= Xen + * +-----+-----+----+----+----+-----+----+----+ * * The lookup of this index table translates to looking up * Bit 7, Bit 4, and Bit 3 of val entry: