From: Julien Grall Date: Tue, 12 Sep 2017 10:03:14 +0000 (+0100) Subject: xen/arm: Add FnV field in hsr_*abt X-Git-Tag: archive/raspbian/4.11.1-1+rpi1~1^2~66^2~1382 X-Git-Url: https://dgit.raspbian.org/?a=commitdiff_plain;h=2994b8c32714300405f8780590a590b97d2a942c;p=xen.git xen/arm: Add FnV field in hsr_*abt FnV (FAR not Valid) bit was introduced by ARMv8 in both AArch32 and AArch64 (See D7-2275, D7-2277, G6-4958, G6-4962 in ARM DDI 0487B.a). Note the new revision of ARMv8 defined more bits in HSR. They haven't been added at the moment because we have no use of them in Xen. Signed-off-by: Julien Grall Reviewed-by: Andre Przywara Acked-by: Stefano Stabellini Signed-off-by: Stefano Stabellini --- diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index c0b4c3d1c9..6d7f9505d0 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -585,7 +585,8 @@ union hsr { unsigned long s1ptw:1; /* Stage 2 fault during stage 1 translation */ unsigned long res1:1; /* RES0 */ unsigned long eat:1; /* External abort type */ - unsigned long res2:15; + unsigned long fnv:1; /* FAR not Valid */ + unsigned long res2:14; unsigned long len:1; /* Instruction length */ unsigned long ec:6; /* Exception Class */ } iabt; /* HSR_EC_INSTR_ABORT_* */ @@ -596,10 +597,11 @@ union hsr { unsigned long s1ptw:1; /* Stage 2 fault during stage 1 translation */ unsigned long cache:1; /* Cache Maintenance */ unsigned long eat:1; /* External Abort Type */ + unsigned long fnv:1; /* FAR not Valid */ #ifdef CONFIG_ARM_32 - unsigned long sbzp0:6; + unsigned long sbzp0:5; #else - unsigned long sbzp0:4; + unsigned long sbzp0:3; unsigned long ar:1; /* Acquire Release */ unsigned long sf:1; /* Sixty Four bit register */ #endif