From: Jan Beulich Date: Tue, 13 Apr 2021 08:16:06 +0000 (+0200) Subject: VT-d: qinval indexes are only up to 19 bits wide X-Git-Tag: archive/raspbian/4.16.0+51-g0941d6cb-1+rpi1~2^2~42^2~706 X-Git-Url: https://dgit.raspbian.org/?a=commitdiff_plain;h=1b5d913fa0b3e4b9a8bba10c1db83082193bcc7a;p=xen.git VT-d: qinval indexes are only up to 19 bits wide There's no need for 64-bit accesses to these registers (outside of initial setup and dumping). Also remove some stray blanks. Signed-off-by: Jan Beulich Reviewed-by: Kevin Tian --- diff --git a/xen/drivers/passthrough/vtd/qinval.c b/xen/drivers/passthrough/vtd/qinval.c index 6100e778f3..c0ea19d4bd 100644 --- a/xen/drivers/passthrough/vtd/qinval.c +++ b/xen/drivers/passthrough/vtd/qinval.c @@ -42,14 +42,13 @@ static void print_qi_regs(const struct vtd_iommu *iommu) static unsigned int qinval_next_index(struct vtd_iommu *iommu) { - u64 tail; + unsigned int tail = dmar_readl(iommu->reg, DMAR_IQT_REG); - tail = dmar_readq(iommu->reg, DMAR_IQT_REG); tail >>= QINVAL_INDEX_SHIFT; /* (tail+1 == head) indicates a full queue, wait for HW */ - while ( ( tail + 1 ) % QINVAL_ENTRY_NR == - ( dmar_readq(iommu->reg, DMAR_IQH_REG) >> QINVAL_INDEX_SHIFT ) ) + while ( (tail + 1) % QINVAL_ENTRY_NR == + (dmar_readl(iommu->reg, DMAR_IQH_REG) >> QINVAL_INDEX_SHIFT) ) cpu_relax(); return tail; @@ -57,12 +56,12 @@ static unsigned int qinval_next_index(struct vtd_iommu *iommu) static void qinval_update_qtail(struct vtd_iommu *iommu, unsigned int index) { - u64 val; + unsigned int val; /* Need hold register lock when update tail */ ASSERT( spin_is_locked(&iommu->register_lock) ); val = (index + 1) % QINVAL_ENTRY_NR; - dmar_writeq(iommu->reg, DMAR_IQT_REG, (val << QINVAL_INDEX_SHIFT)); + dmar_writel(iommu->reg, DMAR_IQT_REG, val << QINVAL_INDEX_SHIFT); } static int __must_check queue_invalidate_context_sync(struct vtd_iommu *iommu,