From: Ian Campbell Date: Mon, 30 Mar 2015 12:42:52 +0000 (+0100) Subject: xen: arm: Annotate registers trapped by HCR_EL1.TIDCP X-Git-Tag: archive/raspbian/4.8.0-1+rpi1~1^2~3305 X-Git-Url: https://dgit.raspbian.org/?a=commitdiff_plain;h=18babb3bf0d160b7146504e1043096482b967543;p=xen.git xen: arm: Annotate registers trapped by HCR_EL1.TIDCP This traps variety of implementation defined registers, so add a note to the default case of the respective handler. Signed-off-by: Ian Campbell Reviewed-by: Julien Grall --- diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 093c2c08b1..728af2e751 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -1705,6 +1705,21 @@ static void do_cp15_32(struct cpu_user_regs *regs, */ return handle_raz_wi(regs, r, cp32.read, hsr, 1); + /* + * HCR_EL2.TIDCP + * + * ARMv7 (DDI 0406C.b): B1.14.3 + * ARMv8 (DDI 0487A.d): D1-1501 Table D1-43 + * + * - CRn==c9, opc1=={0-7}, CRm=={c0-c2, c5-c8}, opc2=={0-7} + * (Cache and TCM lockdown registers) + * - CRn==c10, opc1=={0-7}, CRm=={c0, c1, c4, c8}, opc2=={0-7} + * (VMSA CP15 c10 registers) + * - CRn==c11, opc1=={0-7}, CRm=={c0-c8, c15}, opc2=={0-7} + * (VMSA CP15 c11 registers) + * + * And all other unknown registers. + */ default: gdprintk(XENLOG_ERR, "%s p15, %d, r%d, cr%d, cr%d, %d @ 0x%"PRIregister"\n", @@ -1955,6 +1970,16 @@ static void do_sysreg(struct cpu_user_regs *regs, dprintk(XENLOG_WARNING, "Emulation of sysreg ICC_SGI0R_EL1/ASGI1R_EL1 not supported\n"); return inject_undef64_exception(regs, hsr.len); + + /* + * HCR_EL2.TIDCP + * + * ARMv8 (DDI 0487A.d): D1-1501 Table D1-43 + * + * - Reserved control space for IMPLEMENTATION DEFINED functionality. + * + * And all other unknown registers. + */ default: { const struct hsr_sysreg sysreg = hsr.sysreg;