From: Julien Grall Date: Sat, 16 Jul 2022 14:34:07 +0000 (+0100) Subject: xen/arm: head: Add missing isb after writing to SCTLR_EL2/HSCTLR X-Git-Tag: archive/raspbian/4.16.2-1+rpi1^2~34^2~13 X-Git-Url: https://dgit.raspbian.org/?a=commitdiff_plain;h=0d362e5ed3fa1b307834bcffbf7fd5341e32ebfd;p=xen.git xen/arm: head: Add missing isb after writing to SCTLR_EL2/HSCTLR Write to SCTLR_EL2/HSCTLR may not be visible until the next context synchronization. When initializing the CPU, we want the update to take effect right now. So add an isb afterwards. Spec references: - AArch64: D13.1.2 ARM DDI 0406C.d - AArch32 v8: G8.1.2 ARM DDI 0406C.d - AArch32 v7: B5.6.3 ARM DDI 0406C.d Signed-off-by: Julien Grall Reviewed-by: Michal Orzel Reviewed-by: Bertrand Marquis (cherry picked from commit 25424d1a6b7b7e875230aba77c2f044a4883e49a) --- diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S index 7178865f48..854481f4f9 100644 --- a/xen/arch/arm/arm32/head.S +++ b/xen/arch/arm/arm32/head.S @@ -353,6 +353,7 @@ cpu_init_done: ldr r0, =HSCTLR_SET mcr CP32(r0, HSCTLR) + isb mov pc, r5 /* Return address is in r5 */ ENDPROC(cpu_init) diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index 057dd5d925..42a2177c53 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -485,6 +485,7 @@ cpu_init: ldr x0, =SCTLR_EL2_SET msr SCTLR_EL2, x0 + isb /* * Ensure that any exceptions encountered at EL2