From: Jan Beulich Date: Tue, 29 May 2018 10:39:24 +0000 (+0200) Subject: x86/CPUID: don't override tool stack decision to hide STIBP X-Git-Tag: archive/raspbian/4.11.1-1+rpi1~1^2~66^2~74 X-Git-Url: https://dgit.raspbian.org/?a=commitdiff_plain;h=06f542f8f2e446c01bd0edab51e9450af7f6e05b;p=xen.git x86/CPUID: don't override tool stack decision to hide STIBP Other than in the feature sets, where we indeed want to offer the feature even if not enumerated on hardware, we shouldn't dictate the feature being available if tool stack or host admin have decided to not expose it (for whatever [questionable?] reason). That feature set side override is sufficient to achieve the intended guest side safety property (in offering - by default - STIBP independent of actual availability in hardware). Signed-off-by: Jan Beulich Reviewed-by: Andrew Cooper Release-acked-by: Juergen Gross --- diff --git a/xen/arch/x86/cpuid.c b/xen/arch/x86/cpuid.c index 4b8d33013f..beee47d0ed 100644 --- a/xen/arch/x86/cpuid.c +++ b/xen/arch/x86/cpuid.c @@ -642,14 +642,6 @@ void recalculate_cpuid_policy(struct domain *d) recalculate_xstate(p); recalculate_misc(p); - /* - * Override STIBP to match IBRS. Guests can safely use STIBP - * functionality on non-HT hardware, but can't necesserily protect - * themselves from SP2/Spectre/Branch Target Injection if STIBP is hidden - * on HT-capable hardware. - */ - p->feat.stibp = p->feat.ibrsb; - for ( i = 0; i < ARRAY_SIZE(p->cache.raw); ++i ) { if ( p->cache.subleaf[i].type >= 1 && diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h index c721c125ab..f1a5ed93e0 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -243,7 +243,7 @@ XEN_CPUFEATURE(IBPB, 8*32+12) /*A IBPB support only (no IBRS, used by XEN_CPUFEATURE(AVX512_4VNNIW, 9*32+ 2) /*A AVX512 Neural Network Instructions */ XEN_CPUFEATURE(AVX512_4FMAPS, 9*32+ 3) /*A AVX512 Multiply Accumulation Single Precision */ XEN_CPUFEATURE(IBRSB, 9*32+26) /*A IBRS and IBPB support (used by Intel) */ -XEN_CPUFEATURE(STIBP, 9*32+27) /*A! STIBP */ +XEN_CPUFEATURE(STIBP, 9*32+27) /*A STIBP */ XEN_CPUFEATURE(ARCH_CAPS, 9*32+29) /* IA32_ARCH_CAPABILITIES MSR */ XEN_CPUFEATURE(SSBD, 9*32+31) /*A MSR_SPEC_CTRL.SSBD available */