s8 __read_mostly opt_allow_unsafe;
boolean_param("allow_unsafe", opt_allow_unsafe);
+/* Signal whether the ACPI C1E quirk is required. */
+bool __read_mostly amd_acpi_c1e_quirk;
+
static inline int rdmsr_amd_safe(unsigned int msr, unsigned int *lo,
unsigned int *hi)
{
smp_processor_id(), msr_content);
}
-static void check_disable_c1e(unsigned int port, u8 value)
+void amd_check_disable_c1e(unsigned int port, u8 value)
{
/* C1E is sometimes enabled during entry to ACPI mode. */
if ((port == acpi_smi_cmd) && (value == acpi_enable_value))
{
case 0xf ... 0x17:
disable_c1e(NULL);
- if (acpi_smi_cmd && (acpi_enable_value | acpi_disable_value))
- pv_post_outb_hook = check_disable_c1e;
+ if (acpi_smi_cmd && (acpi_enable_value | acpi_disable_value)) {
+ pv_post_outb_hook = amd_check_disable_c1e;
+ amd_acpi_c1e_quirk = true;
+ }
break;
}
#include <xen/sched-if.h>
#include <xen/softirq.h>
+#include <asm/amd.h>
#include <asm/dom0_build.h>
#include <asm/guest.h>
#include <asm/hpet.h>
rc |= ioports_deny_access(d, 0xcfc, 0xcff);
#ifdef CONFIG_HVM
if ( is_hvm_domain(d) )
+ {
/* HVM debug console IO port. */
rc |= ioports_deny_access(d, XEN_HVM_DEBUGCONS_IOPORT,
XEN_HVM_DEBUGCONS_IOPORT);
+ if ( amd_acpi_c1e_quirk )
+ rc |= ioports_deny_access(d, acpi_smi_cmd, acpi_smi_cmd);
+ }
#endif
/* Command-line I/O ranges. */
process_dom0_ioports_disable(d);
spin_unlock(&osvw_lock);
}
+static int acpi_c1e_quirk(int dir, unsigned int port, unsigned int bytes,
+ uint32_t *val)
+{
+ ASSERT(bytes == 1 && port == acpi_smi_cmd);
+
+ if ( dir == IOREQ_READ )
+ *val = inb(port);
+ else
+ {
+ outb(*val, port);
+ amd_check_disable_c1e(port, *val);
+ }
+
+ return X86EMUL_OKAY;
+}
+
static int svm_domain_initialise(struct domain *d)
{
static const struct arch_csw csw = {
svm_guest_osvw_init(d);
+ if ( is_hardware_domain(d) && amd_acpi_c1e_quirk )
+ register_portio_handler(d, acpi_smi_cmd, 1, acpi_c1e_quirk);
+
return 0;
}
void fam10h_check_enable_mmcfg(void);
void check_enable_amd_mmconf_dmi(void);
+extern bool amd_acpi_c1e_quirk;
+void amd_check_disable_c1e(unsigned int port, u8 value);
+
#endif /* __AMD_H__ */