powerpc/lib/sstep: Fix building for powerpcspe

On powerpcspe, ptesync is not a recognised instruction and so fails to
assemble. We don't expect to have to emulate an lwsync or a ptesync on a
32-bit kernel, so just ifdef them out, and catch any unexpected barrier
types.

Fixes: 3cdfcbfd32b9 ("powerpc: Change analyse_instr so it doesn't modify *regs")
Signed-off-by: James Clarke <jrtc27@jrtc27.com>
Gbp-Pq: Topic bugfix/powerpc
Gbp-Pq: Name powerpc-lib-sstep-fix-building-for-powerpcspe.patch

diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index c077acb983a19f8831bd46cbb8ec2d5e051d4974..e04b4ecbf7929603e9bef77d028bac45f9461fb4 100644 (file)
--- a/arch/powerpc/lib/sstep.c
+++ b/arch/powerpc/lib/sstep.c
@@ -2787,12 +2787,16 @@ void emulate_update_regs(struct pt_regs *regs, struct instruction_op *op)
                case BARRIER_EIEIO:
                        eieio();
                        break;
+#ifdef __powerpc64__
                case BARRIER_LWSYNC:
                        asm volatile("lwsync" : : : "memory");
                        break;
                case BARRIER_PTESYNC:
                        asm volatile("ptesync" : : : "memory");
                        break;
+#endif
+               default:
+                       WARN_ON_ONCE(1);
                }
                break;