DEFINE_MAPPED_REG_OFS(XSI_IHA_OFS, iha);
DEFINE_MAPPED_REG_OFS(XSI_ITIR_OFS, itir);
DEFINE_MAPPED_REG_OFS(XSI_PSR_IC_OFS, interrupt_collection_enabled);
- DEFINE_MAPPED_REG_OFS(XSI_INCOMPL_REGFR_OFS, incomplete_regframe);
DEFINE_MAPPED_REG_OFS(XSI_BANKNUM_OFS, banknum);
DEFINE_MAPPED_REG_OFS(XSI_BANK0_R16_OFS, bank0_regs[0]);
DEFINE_MAPPED_REG_OFS(XSI_BANK1_R16_OFS, bank1_regs[0]);
.mem.offset 8,0; st8.spill [r17]=r11,24; \
;; \
/* xen special handling for possibly lazy cover */ \
- movl r8=XSI_INCOMPL_REGFR; \
- ;; \
- ld4 r30=[r8]; \
- ;; \
- /* set XSI_INCOMPL_REGFR 0 */ \
- st4 [r8]=r0; \
- cmp.eq p6,p7=r30,r0; \
- ;; /* not sure if this stop bit is necessary */ \
-(p6) adds r8=XSI_PRECOVER_IFS-XSI_INCOMPL_REGFR,r8; \
-(p7) adds r8=XSI_IFS-XSI_INCOMPL_REGFR,r8; \
+ movl r8=XSI_PRECOVER_IFS; \
;; \
ld8 r30=[r8]; \
;; \
#define XSI_IFS (XSI_BASE + XSI_IFS_OFS)
#define XSI_PRECOVER_IFS (XSI_BASE + XSI_PRECOVER_IFS_OFS)
-#define XSI_INCOMPL_REGFR (XSI_BASE + XSI_INCOMPL_REGFR_OFS)
#define XSI_IFA (XSI_BASE + XSI_IFA_OFS)
#define XSI_ISR (XSI_BASE + XSI_ISR_OFS)
#define XSI_IIM (XSI_BASE + XSI_IIM_OFS)
DEFINE_MAPPED_REG_OFS(XSI_ITV_OFS, itv);
DEFINE_MAPPED_REG_OFS(XSI_PTA_OFS, pta);
DEFINE_MAPPED_REG_OFS(XSI_PSR_IC_OFS, interrupt_collection_enabled);
- DEFINE_MAPPED_REG_OFS(XSI_INCOMPL_REGFR_OFS, incomplete_regframe);
DEFINE_MAPPED_REG_OFS(XSI_METAPHYS_OFS, metaphysical_mode);
DEFINE_MAPPED_REG_OFS(XSI_BANKNUM_OFS, banknum);
DEFINE_MAPPED_REG_OFS(XSI_BANK0_R16_OFS, bank0_regs[0]);
PSCB(v, isr) = isr;
PSCB(v, iip) = regs->cr_iip;
PSCB(v, ifs) = 0;
- PSCB(v, incomplete_regframe) = 0;
regs->cr_iip = ((unsigned long)PSCBX(v, iva) + vector) & ~0xffUL;
regs->cr_ipsr = (regs->cr_ipsr & ~DELIVER_PSR_CLR) | DELIVER_PSR_SET;
PSCB(v, isr) = isr;
PSCB(v, iip) = regs->cr_iip;
PSCB(v, ifs) = 0;
- PSCB(v, incomplete_regframe) = 0;
regs->cr_iip = v->arch.event_callback_ip;
regs->cr_ipsr = (regs->cr_ipsr & ~DELIVER_PSR_CLR) | DELIVER_PSR_SET;
{
if (!PSCB(v, interrupt_collection_enabled)) {
PSCB(v, ifs) = regs->cr_ifs;
- PSCB(v, incomplete_regframe) = 1;
regs->cr_ifs = 0;
perfc_incrc(lazy_cover);
return 1; // retry same instruction with cr.ifs off
// and isr.ri to cr.isr.ri (all other bits zero)
// - cover and set shared_mem precover_ifs to cr.ifs
// ^^^ MISSED THIS FOR fast_break??
-// - set shared_mem ifs and incomplete_regframe to 0
// - set shared_mem interrupt_delivery_enabled to 0
// - set shared_mem interrupt_collection_enabled to 0
// - set r31 to SHAREDINFO_ADDR
st1 [r22]=r20
st4 [r18]=r0
// cover and set shared_mem precover_ifs to cr.ifs
- // set shared_mem ifs and incomplete_regframe to 0
+ // set shared_mem ifs to 0
cover ;;
mov r20=cr.ifs;;
- adds r21=XSI_INCOMPL_REGFR_OFS-XSI_PSR_IC_OFS,r18 ;;
- st4 [r21]=r0 ;;
adds r21=XSI_IFS_OFS-XSI_PSR_IC_OFS,r18 ;;
st8 [r21]=r0 ;;
adds r21=XSI_PRECOVER_IFS_OFS-XSI_PSR_IC_OFS,r18 ;;
st1 [r22]=r20;;
st4 [r18]=r0;;
// cover and set shared_mem precover_ifs to cr.ifs
- // set shared_mem ifs and incomplete_regframe to 0
+ // set shared_mem ifs to 0
cover ;;
mov r20=cr.ifs;;
- adds r21=XSI_INCOMPL_REGFR_OFS-XSI_PSR_IC_OFS,r18 ;;
- st4 [r21]=r0 ;;
adds r21=XSI_IFS_OFS-XSI_PSR_IC_OFS,r18 ;;
st8 [r21]=r0 ;;
adds r21=XSI_PRECOVER_IFS_OFS-XSI_PSR_IC_OFS,r18 ;;
st1 [r24]=r22
st4 [r18]=r0;;
// cover and set shared_mem precover_ifs to cr.ifs
- // set shared_mem ifs and incomplete_regframe to 0
+ // set shared_mem ifs to 0
cover ;;
mov r24=cr.ifs;;
- adds r21=XSI_INCOMPL_REGFR_OFS-XSI_PSR_IC_OFS,r18 ;;
- st4 [r21]=r0 ;;
adds r21=XSI_IFS_OFS-XSI_PSR_IC_OFS,r18 ;;
st8 [r21]=r0 ;;
adds r21=XSI_PRECOVER_IFS_OFS-XSI_PSR_IC_OFS,r18 ;;
just_do_rfi:
// r18=&vpsr.i|vpsr.ic, r21==vpsr, r22=vcr.iip
mov cr.iip=r22;;
- adds r20=XSI_INCOMPL_REGFR_OFS-XSI_PSR_IC_OFS,r18 ;;
- st4 [r20]=r0 ;;
adds r20=XSI_IFS_OFS-XSI_PSR_IC_OFS,r18 ;;
ld8 r20=[r20];;
dep r20=0,r20,38,25;; // ensure ifs has no reserved bits set
st1 [r22]=r20
st4 [r18]=r0;;
// cover and set shared_mem precover_ifs to cr.ifs
- // set shared_mem ifs and incomplete_regframe to 0
+ // set shared_mem ifs to 0
#if 0
cover ;;
mov r20=cr.ifs;;
- adds r22=XSI_INCOMPL_REG_OFS-XSI_PSR_IC_OFS,r18 ;;
- st4 [r22]=r0 ;;
adds r22=XSI_IFS_OFS-XSI_PSR_IC_OFS,r18 ;;
st8 [r22]=r0 ;;
adds r22=XSI_PRECOVER_IFS_OFS-XSI_PSR_IC_OFS,r18 ;;
st8 [r22]=r20 ;;
// leave cr.ifs alone for later rfi
#else
- adds r22=XSI_INCOMPL_REG_OFS-XSI_PSR_IC_OFS,r18 ;;
- st4 [r22]=r0 ;;
adds r22=XSI_IFS_OFS-XSI_PSR_IC_OFS,r18 ;;
ld8 r20=[r22];;
st8 [r22]=r0 ;;
mov r25=cr.iip;;
// skip test for vpsr.ic.. it's a prerequisite for hyperprivops
cover ;;
- adds r20=XSI_INCOMPL_REGFR_OFS-XSI_PSR_IC_OFS,r18 ;;
- mov r30=cr.ifs;;
- adds r22=XSI_IFS_OFS-XSI_PSR_IC_OFS,r18
- ld4 r21=[r20] ;;
- cmp.eq p6,p7=r21,r0 ;;
-(p6) st8 [r22]=r30;;
-(p7) st4 [r20]=r0;;
+ mov r30=cr.ifs
+ adds r22=XSI_IFS_OFS-XSI_PSR_IC_OFS,r18;;
+ st8 [r22]=r30;;
mov cr.ifs=r0;;
// adjust return address to skip over break instruction
extr.u r26=r24,41,2 ;;
//PSCB(vcpu,ifs) = PSCB(vcpu)->regs.cr_ifs;
//*pval = PSCB(vcpu,regs).cr_ifs;
*pval = PSCB(vcpu, ifs);
- PSCB(vcpu, incomplete_regframe) = 0;
return IA64_NO_FAULT;
}
printk("*** DOMAIN TRYING TO TURN ON BIG-ENDIAN!!!\n");
return IA64_ILLOP_FAULT;
}
- PSCB(vcpu, incomplete_regframe) = 0; // is this necessary?
ifs = PSCB(vcpu, ifs);
if (ifs > 0x8000000000000000UL) {
REGS *regs = vcpu_regs(vcpu);
if (!PSCB(vcpu, interrupt_collection_enabled)) {
- if (!PSCB(vcpu, incomplete_regframe))
- PSCB(vcpu, ifs) = regs->cr_ifs;
- else
- PSCB(vcpu, incomplete_regframe) = 0;
+ PSCB(vcpu, ifs) = regs->cr_ifs;
}
regs->cr_ifs = 0;
return IA64_NO_FAULT;
*/
unsigned char *interrupt_mask_addr;
int pending_interruption;
- int incomplete_regframe; // see SDM vol2 6.8
unsigned char vpsr_pp;
- unsigned char reserved5_2[7];
- unsigned long reserved5_1[3];
+ unsigned char reserved5_2[3];
+ unsigned long reserved5_1[4];
int metaphysical_mode; // 1 = use metaphys mapping, 0 = use virtual
int banknum; // 0 or 1, which virtual register bank is active
unsigned long rrs[8]; // region registers