RETURN1(make_longfloat(*(double *)addr));
}
-DEFUN_NEW("FEENABLEEXCEPT",fixnum,fSfeenableexcept,SI,1,1,NONE,II,OO,OO,OO,(fixnum x),"") {
+DEFUN_NEW("FEENABLEEXCEPT",object,fSfeenableexcept,SI,1,1,NONE,II,OO,OO,OO,(fixnum x),"") {
#ifdef HAVE_FEENABLEEXCEPT
}
#endif
- RETURN1(x);
+ RETURN1((object)x);
}
-DEFUN_NEW("FEDISABLEEXCEPT",fixnum,fSfedisableexcept,SI,0,0,NONE,IO,OO,OO,OO,(void),"") {
+DEFUN_NEW("FEDISABLEEXCEPT",object,fSfedisableexcept,SI,0,0,NONE,IO,OO,OO,OO,(void),"") {
fixnum x;
}
#endif
- RETURN1(x);
+ RETURN1((object)x);
}
#if defined(__x86_64__) || defined(__i386__)
#define FE_TEST(x87sw_,mxcsr_,excepts_) ((x87sw_)&(excepts_))|(~((mxcsr_)>>7)&excepts_)
-DEFUN_NEW("FPE_CODE",fixnum,fSfpe_code,SI,2,2,NONE,II,OO,OO,OO,(fixnum x87sw,fixnum mxcsr),"") {
+DEFUN_NEW("FPE_CODE",object,fSfpe_code,SI,2,2,NONE,II,OO,OO,OO,(fixnum x87sw,fixnum mxcsr),"") {
- RETURN1(FE_TEST(x87sw,mxcsr,FE_INVALID) ? FPE_FLTINV :
- (FE_TEST(x87sw,mxcsr,FE_DIVBYZERO) ? FPE_FLTDIV :
- (FE_TEST(x87sw,mxcsr,FE_OVERFLOW) ? FPE_FLTOVF :
- (FE_TEST(x87sw,mxcsr,FE_UNDERFLOW) ? FPE_FLTUND :
- (FE_TEST(x87sw,mxcsr,FE_INEXACT) ? FPE_FLTRES : 0)))));
+ RETURN1((object)(FE_TEST(x87sw,mxcsr,FE_INVALID) ? FPE_FLTINV :
+ (FE_TEST(x87sw,mxcsr,FE_DIVBYZERO) ? FPE_FLTDIV :
+ (FE_TEST(x87sw,mxcsr,FE_OVERFLOW) ? FPE_FLTOVF :
+ (FE_TEST(x87sw,mxcsr,FE_UNDERFLOW) ? FPE_FLTUND :
+ (FE_TEST(x87sw,mxcsr,FE_INEXACT) ? FPE_FLTRES : 0))))));
}
#if defined(__MINGW32__) || defined(__CYGWIN__)
-DEFUN_NEW("FNSTSW",fixnum,fSfnstsw,SI,0,0,NONE,II,OO,OO,OO,(void),"") {
+DEFUN_NEW("FNSTSW",object,fSfnstsw,SI,0,0,NONE,II,OO,OO,OO,(void),"") {
volatile unsigned short t;
ASM ("fnstsw %0" :: "m" (t));
- RETURN1(t);
+ RETURN1((object)t);
}
-DEFUN_NEW("STMXCSR",fixnum,fSstmxcsr,SI,0,0,NONE,II,OO,OO,OO,(void),"") {
+DEFUN_NEW("STMXCSR",object,fSstmxcsr,SI,0,0,NONE,II,OO,OO,OO,(void),"") {
volatile unsigned int t;
ASM ("stmxcsr %0" :: "m" (t));
- RETURN1(t);
+ RETURN1((object)t);
}
#endif